English
Process Detector (For DVFS and monitoring process variation)
Analog behavioral models reduce mixed-signal LSI verification time
By Takao Ito, Chief Specialist, Toshiba Corporation
Jun 22, 2007 (12:52 PM) -- Planet Analog
Figure 1a: CPU performance and simulation verification trend; taller (blue) bars are CPU performance, lower (yellow) bars are verification times
Figure 1b: Verification time trend
Jun 22, 2007 (12:52 PM) -- Planet Analog
Smaller process geometries are making it possible to take analog components off the board and incorporate them into the chip together with the digital portions of the designs, increasing the complexity of circuits. Even though there is a rapid increase in today's processor performance, simulation for full-chip verification is still taking a long time (Figure 1a and Figure 1b).
Figure 1a: CPU performance and simulation verification trend; taller (blue) bars are CPU performance, lower (yellow) bars are verification times
Figure 1b: Verification time trend
Current methodologies are no longer sufficient or acceptable, so new verification methods are needed.
|
E-mail This Article | 
|
|
Printer-Friendly Page |
Related Articles
- Mixed-signal SOC verification using analog behavioral models
- Efficient Verification and Virtual Prototyping of Analog and Mixed-Signal IP and SOCs Using Behavioral Models
- Mixed-Signal Verification for USB 2.0 Physical Layer IP
- Analog and Mixed-Signal Connectivity IP at 65nm and below
- Improve performance and reduce power consumption in mixed-signal designs
New Articles
- Why RISC-V is a viable option for safety-critical applications
- Dimensioning in 3D space: Object Volumetric Measurement by Leveraging Depth Camera-based Reconstruction on NVIDIA Edge devices
- What is JESD204B? Quick summary of the standard
- Post-Quantum Cryptography - Securing Semiconductors in a Post-Quantum World
- Analysis and Summary on Clock Generator Circuits and PLL Design
Most Popular
- System Verilog Assertions Simplified
- Enhancing VLSI Design Efficiency: Tackling Congestion and Shorts with Practical Approaches and PnR Tool (ICC2)
- System Verilog Macro: A Powerful Feature for Design Verification Projects
- Method for Booting ARM Based Multi-Core SoCs
- An Outline of the Semiconductor Chip Design Flow