Compiler optimization for DSP applications
By Eran Belaish, CEVA
Jul 23 2007 (3:00 AM) -- Embedded.com
As DSP processors become more and more powerful, the portion of code that can remain at the C level increases. However, compilers cannot produce optimized code without assistance from the programmer. To maximize the performance, the programmer must tune the compiler using various compilation options.
Unfortunately, it is quite common to find DSP applications that don't take advantage of the tuning capabilities of the compiler. Instead, they are compiled with the same set of compilation options throughout the whole application. This method ignores the special needs of each function.
Smart selection of compilation options can yield a dramatic code performance improvement. For example, code size can be greatly reduced. This is often a major factor when evaluating the cost of a product, as it has a direct influence on the amount of memory required. This article shows how to improve code size consumption as well as the consumption of other important resources.
![]() |
E-mail This Article | ![]() |
![]() |
Printer-Friendly Page |
|
Ceva, Inc. Hot IP
Related Articles
- Optimizing High Performance CPUs, GPUs and DSPs? Use logic and memory IP - Part II
- Architecture-oriented C optimization, part 1: DSP features
- Using the ARM Cortex-R4 for DSP, part 2: Software optimization
- DSP optimization strategies using simulators and profilers
- How to exploit 17 tried and true DSP power optimization techniques for wireless applications
New Articles
- Why RISC-V is a viable option for safety-critical applications
- Dimensioning in 3D space: Object Volumetric Measurement by Leveraging Depth Camera-based Reconstruction on NVIDIA Edge devices
- What is JESD204B? Quick summary of the standard
- Post-Quantum Cryptography - Securing Semiconductors in a Post-Quantum World
- Analysis and Summary on Clock Generator Circuits and PLL Design
Most Popular
- System Verilog Assertions Simplified
- Enhancing VLSI Design Efficiency: Tackling Congestion and Shorts with Practical Approaches and PnR Tool (ICC2)
- System Verilog Macro: A Powerful Feature for Design Verification Projects
- Method for Booting ARM Based Multi-Core SoCs
- An Outline of the Semiconductor Chip Design Flow