In-System Silicon Validation and Debug -- Part 3: Silicon Experience

By Miron Abramovici and Paul Bradley, Dafca
October 15, 2007 -- edadesignline.com

This is the third and final article in a series about silicon validation. Part 1 described the silicon validation problem and the basic requirements of an effective and scalable solution. Part 2 introduced the new approach and its basic applications. Part 3 presents the experience provided by four commercial devices implemented with the ClearBlue solution.

You can read Part 1 here
And Part 2 here

Silicon Experience
As described previously, the ClearBlue solution developed by DAFCA, Inc., provides designers with a means to tailor their on-chip instrumentation to a variety of post-silicon validation requirements and applications.

ClearBlue technology has proven successful in the following applications:

Validation of complex IP cores " ClearBlue enabled the IP developers to rapidly validate and certify their IP in a real-world environment (i.e., on chip, at speed), and also facilitated their customer in quickly isolating problems encountered during IP integration and testing.
Validation and debug infrastructure for Platform SoCs " ClearBlue provided a reconfigurable infrastructure for validation and debugging of Platform SoCs, as well as an extendable instrumentation scheme and a comprehensive set of applications for Platform SoC users. Instrumenting the Platform SoC significantly reduces the instrumentation effort for all the customers adopting it.
On-chip stress testing and fault injection " ClearBlue provided a transaction-level and bit-level means to create comprehensive stress conditions and fault conditions in select circuitry and to analyze subsequent hardware, software, and system consequences. Such tests commenced almost immediately upon the availability of first silicon and were not restricted to digital logic; for example, stress and fault conditions were applied and observed at A/D and D/A boundaries.
Distributed multi-clock domain logic analysis " The distributed instruments were programmed for logic analysis that supported cross triggers, and were subsequently reprogrammed for use in performance monitoring and in-silicon assertions during normal system operation without modifying behavior or degrading performance.
System bus and peripheral monitoring " ClearBlue provided transaction-level visibility and control of an embedded processor complex that included instruction buses, data buses, shared resources, and peripherals. The solution provided visibility beyond traditional instruction tracing and included system-wide monitoring and analysis functions, enabling a means to analyze complex system events and to correlate hardware and software activity.

This diversity in application is evident in the four devices presented below. Each of these devices was implemented within a standard ASIC flow using tools from Cadence, Magma, Mentor Graphics, and Synopsys.

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