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The Case for DDR-XAUI
Ori Aruj, Dune Networks
Oct 11, 2007 (8:15 PM) -- commsdesign.com
Recent developments in the networking and silicon markets are driving the support of multiple ports of 10 Gigabit Ethernet to the limit. High levels of integration dictate that large numbers of XAUI interfaces must be integrated in silicon to a level where silicon devices are bound by their external interface limitations rather then their internal bandwidth.
In order to minimize the number of SerDes lanes, higher speed lanes are required. The options available today are 6.25Gbps and 10Gbps (XFI) lanes. This article argues that there is a strong business case for DDR-XAUI, a two lane 6.25Gbps XAUI in addition to XFI.
XAUI is an important compatibility interface for 10 Gigabit Ethernet component and system implementers. It provides the low pin-count and long board trace lengths that system vendors need to drive down port costs.
XAUI supports 10Gbps by using four SerDes 3.125Gbps lanes, each lane encoding data with an 8B/10B code. XAUI reduces 10 Gigabit Ethernet's 72 pin XGMII to 16 pins, enabling higher density and lower cost switching chips and optical transceivers. The lower pin count and longer trace lengths allow a single chip to support multiple 10 Gigabit Ethernet ports.
Oct 11, 2007 (8:15 PM) -- commsdesign.com
Recent developments in the networking and silicon markets are driving the support of multiple ports of 10 Gigabit Ethernet to the limit. High levels of integration dictate that large numbers of XAUI interfaces must be integrated in silicon to a level where silicon devices are bound by their external interface limitations rather then their internal bandwidth.
In order to minimize the number of SerDes lanes, higher speed lanes are required. The options available today are 6.25Gbps and 10Gbps (XFI) lanes. This article argues that there is a strong business case for DDR-XAUI, a two lane 6.25Gbps XAUI in addition to XFI.
XAUI is an important compatibility interface for 10 Gigabit Ethernet component and system implementers. It provides the low pin-count and long board trace lengths that system vendors need to drive down port costs.
XAUI supports 10Gbps by using four SerDes 3.125Gbps lanes, each lane encoding data with an 8B/10B code. XAUI reduces 10 Gigabit Ethernet's 72 pin XGMII to 16 pins, enabling higher density and lower cost switching chips and optical transceivers. The lower pin count and longer trace lengths allow a single chip to support multiple 10 Gigabit Ethernet ports.
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