English
Ensuring high-quality video communications
Jian Wang, Thanh Tran, Pradeep Bardia and Ivan Garcia - Texas Instruments
(10/22/2007 9:00 AM EDT) -- EE Times
As the migration to high definition (HD) picks up speed, video system designers are faced with new challenges related to bandwidth requirements, image quality, transcoding and digital media codec flexibility. These are difficult issues even for relatively closed systems that operate in proximity to each other.
In order of magnitude, more processing power is required to encode and decode HD video than standard-definition (SD) video.Whereas a single DSP can handle a stream of SD video encode/decode, for example, up to five may be needed for HD720p at 30 frames per second (fps), and 12 to 13 DSPs may be required for HD1080p at 30 fps.
No one has a trickier set of problems to solve than designers whose systems interface with the Internet Protocol (IP) network--or private networks--to transmit video to distant endpoints. IP-based videoconferencing is one of the most obvious examples of this application. There are many subsets of video communications, ranging from IP video telephony to sophisticated applications in which enhanced wideband audio, presentation data and video boxes are integral parts of the complete real-time system solution.
In addition to handling the difficult migration from SD to HD video, video communications engineers must find ways to minimize end-to-end latency. Visual artifacts such as distorted video caused by network contention/congestion or inadequate video compression implementations can pose problems, but the most challenging user experience is ensuring a natural video communications flow among partici- pants. The task sets ag- gressive limits on system latency.
(10/22/2007 9:00 AM EDT) -- EE Times
As the migration to high definition (HD) picks up speed, video system designers are faced with new challenges related to bandwidth requirements, image quality, transcoding and digital media codec flexibility. These are difficult issues even for relatively closed systems that operate in proximity to each other.
In order of magnitude, more processing power is required to encode and decode HD video than standard-definition (SD) video.Whereas a single DSP can handle a stream of SD video encode/decode, for example, up to five may be needed for HD720p at 30 frames per second (fps), and 12 to 13 DSPs may be required for HD1080p at 30 fps.
No one has a trickier set of problems to solve than designers whose systems interface with the Internet Protocol (IP) network--or private networks--to transmit video to distant endpoints. IP-based videoconferencing is one of the most obvious examples of this application. There are many subsets of video communications, ranging from IP video telephony to sophisticated applications in which enhanced wideband audio, presentation data and video boxes are integral parts of the complete real-time system solution.
In addition to handling the difficult migration from SD to HD video, video communications engineers must find ways to minimize end-to-end latency. Visual artifacts such as distorted video caused by network contention/congestion or inadequate video compression implementations can pose problems, but the most challenging user experience is ensuring a natural video communications flow among partici- pants. The task sets ag- gressive limits on system latency.
|
E-mail This Article | 
|
|
Printer-Friendly Page |
|
||||||
Related Articles
New Articles
- Quantum Readiness Considerations for Suppliers and Manufacturers
- A Rad Hard ASIC Design Approach: Triple Modular Redundancy (TMR)
- Early Interactive Short Isolation for Faster SoC Verification
- The Ideal Crypto Coprocessor with Root of Trust to Support Customer Complete Full Chip Evaluation: PUFcc gained SESIP and PSA Certified™ Level 3 RoT Component Certification
- Advanced Packaging and Chiplets Can Be for Everyone
Most Popular
- System Verilog Assertions Simplified
- System Verilog Macro: A Powerful Feature for Design Verification Projects
- UPF Constraint coding for SoC - A Case Study
- Dynamic Memory Allocation and Fragmentation in C and C++
- Enhancing VLSI Design Efficiency: Tackling Congestion and Shorts with Practical Approaches and PnR Tool (ICC2)