Define the right approach for DRM
Update: Synopsys Expands Security Solutions with Acquisition of Elliptic Technologies (June 29, 2015)
If implemented properly, the hardware-based approach is the toughest to crack.By Al Hawtin, Elliptic Semiconductor and Craig Zajac, Impinj
(10/24/07, 02:02:00 PM EDT) -- Embedded.com
It's become the norm for digital rights management (DRM) designs to be cracked shortly after they're introduced. Among the reasons are poor software designs that leave keys exposed, interception of unencrypted content at a vulnerable point in the system, or the use of new and untested ciphers that are compromised.
ABI Research Analyst Steve Wilson believes that this cycle of developing then breaking DRM designs will be overcome through hardware security engines embedded in system-on-chips (SoCs) aimed at consumer electronics. "In today's consumer electronics products, hardware IC features play little role in protecting copyrighted content," observed Wilson. "Popular DRM schemes that depend on secure software implementations such as Windows DRM, Fairplay, and AACS are routinely targeted and hacked. However, processor vendors are enhancing their architectures and embracing security features that will simplify secure software implementations and make it more difficult to copy and share protected content."
![]() |
E-mail This Article | ![]() |
![]() |
Printer-Friendly Page |
|
Related Articles
- A Rad Hard ASIC Design Approach: Triple Modular Redundancy (TMR)
- BCD Technology: A Unified Approach to Analog, Digital, and Power Design
- Select the Right Microcontroller IP for Your High-Integrity SoCs
- A comprehensive approach to enhancing IoT Security with Artificial Intelligence
- It's Just a Jump to the Left, Right? Shift Left in IC Design Enablement
New Articles
- Why RISC-V is a viable option for safety-critical applications
- Dimensioning in 3D space: Object Volumetric Measurement by Leveraging Depth Camera-based Reconstruction on NVIDIA Edge devices
- What is JESD204B? Quick summary of the standard
- Post-Quantum Cryptography - Securing Semiconductors in a Post-Quantum World
- Analysis and Summary on Clock Generator Circuits and PLL Design
Most Popular
- System Verilog Assertions Simplified
- Enhancing VLSI Design Efficiency: Tackling Congestion and Shorts with Practical Approaches and PnR Tool (ICC2)
- System Verilog Macro: A Powerful Feature for Design Verification Projects
- Method for Booting ARM Based Multi-Core SoCs
- An Outline of the Semiconductor Chip Design Flow