By Bob Mullen, Cadence Design Systems
(02/12/08, 08:55:00 AM EST) -- EDA DesignLine
Phase lock loops (PLLs) play a key role in today's thriving RF industry. Commonly employed to address various timing requirements in ASIC designs, these basic building blocks allow designers to multiply clock frequencies, correct clock duty cycles, and cancel out clock distribution delays. Using inexpensive, low-frequency crystals as an off-chip clock source, designers can use PLLs to multiple the frequencies on-chip and produce various high frequency internal clock signals.
While they seem simple enough in structure and function, PLLs present some unique design challenges. Typically these functions include two widely-spaced time constants and a VCO that oscillates thousands of times faster than the reference frequency. In wireless systems, for example, the VCO often oscillates more than 5000 times faster than the reference frequency. But as IC manufacturers move to nanometer-scale process technologies, PLL performance faces increasingly stringent noise limitations. Such factors can introduce time-varying offsets in the phase of the output clock from its ideal value or jitter which can have disastrous effects on internal timing paths. These effects, in turn, can lead to setup time violations or impact off-chip interfaces by creating setup and hold time violations which lead to data transmission errors. Moreover, other issues including instability, inadequate frequency range, locking problems and static-phase offset can also impact PLL design. Ultimately, any failure to properly characterize PLL performance and detect these issues early in the design cycle can lead to major design issues later in the cycle.
Unfortunately, current simulation tools offer only limited help. Designers can use FastSPICE simulations to verify PLL performance at the transistor level. But the real challenge lies in optimizing those simulations. More often than not, the engineer doesn't know when to simulate at the behavioral level and when to simulate at the transistor level, and how each strategy will impact the design. Inevitably designers resort to a transistor-based simulation to ensure high levels of accuracy. But those simulations can take weeks to complete and the designer often ends up with unmanageable results.
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