Reconfigurable radios, part 1: SDR architectures

By A. Dejonghe, PhD; J. Craninckx, PhD.; J. Provoost, L. Van der Perre, PhD
March 31, 2008 -- dspdesignline.com

Introduction

With the advent of new nomadic devices (SmartPhones, PDAs, laptops) and multimedia applications, the requirements for wireless connections are shifting from simple data rate increases to complex and heterogeneous Quality of Service (QoS). And as these devices are battery-powered, the performance requirements come with a severe constraint on energy consumption. This results in a continuously growing gap between the available energy—constrained by the battery technology—and the steeply increasing energy requirements of emerging radio systems. Technology scaling, platform improvements and circuit design progress are not sufficient to bridge this gap; there is a need for holistic system-level strategies. In this article, we advocate a two-step approach. First, energy-scalability is introduced in the design of the radios. Secondly, intelligent run-time control is introduced to enable low power operation, by exploiting this scalability as well as the dynamics in the system. As a result, software defined radios (SDR) can be realized achieving a power consumption which can be comparable with dedicated radio implementations.

Enable flexibility through design
To enable the translation of functional flexibility into energy scalability, the reconfigurable radio (algorithms, architectures, components and circuits) should first be designed accordingly.

For the reconfigurable digital baseband engine, one has to carefully tradeoff flexibility and energy efficiency: flexibility should only be introduced where its impact on the total average power is sufficiently low or where it offers a broad range of control options that can be exploited effectively later in the control step (targeted flexibility). The required sub-functions of the wireless modem should be designed according to their nature (i.e., control or data processing) and flexibility/energy efficiency requirements. This calls for heterogeneous multi-processor system-on-chip (MPSoC) platforms.

For the reconfigurable analog front-end, architectures and circuits should be designed for a broad range of requirements in carrier frequency, channel bandwidth and noise performance with minimal penalty in power consumption, while also offering energy scalability. One way is to equip all building blocks in the RF front-end with configuration "knobs" that allow them to adjust their performance to the requirements of the considered standards, but also to scale their energy consumption to the actual requirements.

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