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7 µW always on Audio feature extraction with filter banks on TSMC 22nm uLL
Viewpoint: Verification flow should be front and center
By Jason Andrews, Cadence Design Systems & Laurent Ducousso, STMicroelectronics
April 04, 2008 -- edadesignline.com
Home video products have required design and verification of software-programmable hardware functions for several years. The latest generation of 65-nm SoCs integrates tens of embedded CPUs, each one running several applications.
The need to better and earlier integrate hardware and software has been evident for a long time, but because of the increase in complexity, the firmware is becoming available later and later, only making the problem worse. Too many integration issues are postponed until silicon is available.
In the past, software for the processors was always treated like a black box. Firmware engineers passed binary files and memory images to verification engineers to be run. Running firmware on a CPU has always violated a key verification premise: whatever is to be verified must be controllable and observable. This lack of control normally results in a large library of tests to be run on the processor that are difficult to sequence with the hardware interactions and that are also difficult to maintain. Without observability, it is difficult to know whether the tests actually verified what they were designed to verify.
Improving the verification methodology requires a solution that exposes all the issues between hardware and software, and one capable of doing it even when not all the firmware is available. The first step toward achieving this goal is examining the architecture of the software. Some projects don't have a well-defined structure with interfaces between layers of software. To improve the methodology for the home video projects, it is necessary to change the firmware design process and define a more formal hardware abstraction layer (HAL) to contain all the software that interfaces directly with the hardware. Once the HAL is documented and coded, verification can be done on top of this interface.
April 04, 2008 -- edadesignline.com
Home video products have required design and verification of software-programmable hardware functions for several years. The latest generation of 65-nm SoCs integrates tens of embedded CPUs, each one running several applications.
The need to better and earlier integrate hardware and software has been evident for a long time, but because of the increase in complexity, the firmware is becoming available later and later, only making the problem worse. Too many integration issues are postponed until silicon is available.
In the past, software for the processors was always treated like a black box. Firmware engineers passed binary files and memory images to verification engineers to be run. Running firmware on a CPU has always violated a key verification premise: whatever is to be verified must be controllable and observable. This lack of control normally results in a large library of tests to be run on the processor that are difficult to sequence with the hardware interactions and that are also difficult to maintain. Without observability, it is difficult to know whether the tests actually verified what they were designed to verify.
Improving the verification methodology requires a solution that exposes all the issues between hardware and software, and one capable of doing it even when not all the firmware is available. The first step toward achieving this goal is examining the architecture of the software. Some projects don't have a well-defined structure with interfaces between layers of software. To improve the methodology for the home video projects, it is necessary to change the firmware design process and define a more formal hardware abstraction layer (HAL) to contain all the software that interfaces directly with the hardware. Once the HAL is documented and coded, verification can be done on top of this interface.
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