How to raise the RTL abstraction level and design conciseness with SystemVerilog - Part 2

By Sachin Kakkar, Sanjay Gupta, Ayan Banerjee, and Rohit Goel, Mentor Graphics

Programmable Logic DesignLine -- (05/14/08, 12:43:00 PM EDT)

As discussed in Part 1, this article proposes four steps to raise the abstraction level of current Verilog HDL designs and provide a phase wise approach to migrate to SystemVerilog.

1. Enhance conciseness and expressiveness of designs.
2. Add built-in checks to avoid design issues.
3. Design efficient FSM and RAM/ROM memory models.
4. Graduate to object oriented generic hardware designs.

In Part 1 we examined Steps1 and 2 – conciseness of expression and built-in code verification. Now, in Part 2, we will elaborate on Steps 3 and 4 and demonstrate how designers can improve code encapsulation, re-use, and consistency in model behavior – all without adversely affecting the quality of results.

Step 3: Design efficient FSMs and RAM/ROM memory models
#1 – Designing finite state machines
SystemVerilog enables modelling at higher levels of abstraction through the use of the following:

1. Strongly typed enumerated types with state encoding.
2. 2-state data types and user defined types.
3. Specialized always_comb, always_latch, and always_ff blocks.
4. Unique and priority case statements.

These enhancements enable accurate modelling that simulate and synthesize correctly with consistent behaviour across all tools.

The new SystemVerilog coding style is also easy to read and maintain compared to the Verilog method of modelling FSM's.

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