English
Design Challenges Drive Need for New Routing Architecture
By Steve Meier, Synopsys
May 27, 2008 -- edadesignline.com
Timing, area, power, and signal integrity have traditionally been the primary objectives of design technology. Increasingly manufacturability and yield have also become critical design objectives, especially for technology nodes at 90 nanometers (nm) and below. To address manufacturability challenges, multiple yield optimization techniques have been added to the design flow. These techniques range from simple ones-such as antenna checking and fixing for overall yield, redundant via insertion for via-related yield, and wire spreading and widening for particle-related yield-to more sophisticated ones at the latest nodes, such as litho-hotspot detection and correction. As yield has been a secondary goal, classic routers have performed these techniques after optimization-the point at which all of the primary design goals have already been met-with the objective of preserving timing while improving yield.
While this methodology has worked well up to the 65nm technology node, it starts to break down at 45nm and below, where making a trade-off between traditional design goals and yield is becoming tougher. At the latest technology nodes, there is limited room to optimize post routing. This leads to a ping-pong effect, where one design goal is optimized while another is not, necessitating much back and forth performing multiple iterations. Simultaneous optimization of yield is becoming increasingly important in order to achieve high Quality of Results (QoR).
To illustrate this with an example, let us consider the redundant via insertion that protects nanometer designs from via failures. Classic routers insert redundant vias post timing optimization. Doing so during place and route is certainly better than inserting redundant vias during physical verification, where the timing impact cannot be estimated. However, since redundant via insertion is done after the design is already routed and optimized, there is limited flexibility for trading off timing and yield. While it is possible to preserve timing, it is often done at the expense of the redundant via rate. To achieve an efficient trade-off between yield and timing, vias and other yield optimizations such as antenna checking and fixing should be performed throughout the routing and optimization flow. In doing so, their impact can be estimated together with other design goals such as timing, area, power, and signal integrity.
May 27, 2008 -- edadesignline.com
Timing, area, power, and signal integrity have traditionally been the primary objectives of design technology. Increasingly manufacturability and yield have also become critical design objectives, especially for technology nodes at 90 nanometers (nm) and below. To address manufacturability challenges, multiple yield optimization techniques have been added to the design flow. These techniques range from simple ones-such as antenna checking and fixing for overall yield, redundant via insertion for via-related yield, and wire spreading and widening for particle-related yield-to more sophisticated ones at the latest nodes, such as litho-hotspot detection and correction. As yield has been a secondary goal, classic routers have performed these techniques after optimization-the point at which all of the primary design goals have already been met-with the objective of preserving timing while improving yield.
While this methodology has worked well up to the 65nm technology node, it starts to break down at 45nm and below, where making a trade-off between traditional design goals and yield is becoming tougher. At the latest technology nodes, there is limited room to optimize post routing. This leads to a ping-pong effect, where one design goal is optimized while another is not, necessitating much back and forth performing multiple iterations. Simultaneous optimization of yield is becoming increasingly important in order to achieve high Quality of Results (QoR).
To illustrate this with an example, let us consider the redundant via insertion that protects nanometer designs from via failures. Classic routers insert redundant vias post timing optimization. Doing so during place and route is certainly better than inserting redundant vias during physical verification, where the timing impact cannot be estimated. However, since redundant via insertion is done after the design is already routed and optimized, there is limited flexibility for trading off timing and yield. While it is possible to preserve timing, it is often done at the expense of the redundant via rate. To achieve an efficient trade-off between yield and timing, vias and other yield optimizations such as antenna checking and fixing should be performed throughout the routing and optimization flow. In doing so, their impact can be estimated together with other design goals such as timing, area, power, and signal integrity.
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