Aeonic Generate Digital PLL for multi-instance, core logic clocking
Enhance circuit timing design with programmable clock generators (Part 2 of 2)
Planet Analog (06/04/08, 12:00:00 PM EDT)
As clocks speed increase and the number of clocks increases, a programmable clock generator may offer a better system and EMI design solution
EMI reduction with spread-spectrum clocking
To resolve the second practical issue of noise interference, the mutual interference among clocks and other signals could be reduced through good layout and shielding. Different from these methods that passively bypass EMI, changing the clock signal itself through spread-spectrum clocking (SSC) helps actively reduce the EMI generation and is much cheaper and flexible with today's IC capabilities.
SSC simply alters the clock spectrum by spreading the concentrated clock energy over a wider frequency band, without putting enough energy into any one band to exceed the statutory limits. For electronic equipment with sensitivity to a narrowband of frequencies, SSC helps to generate less interference. Figure 3 demonstrates the clock's spectrum before and after spreading. After SSC, the energy is more evenly distributed with no peak above the allowed limit.
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