Low Power High Speed All Digital Phase Locked Loops

By Ankesh Jain, Anubhav Srivastava, Sunny Arora
Freescale semiconductor
Noida, India

Abstract :

 In this paper an All Digital phase locked loop is proposed. This PLL can accomplish faster phase lock.  Additionally, the functions of frequency comparator and phase detector have been improved and are well synchronized. A digital controlled oscillator (DCO) also is proposed for low power and small area for a frequency range of 100MHz to 200 MHz with a power supply less than 1.5v. The proposed ADPLL can be implemented with standard cells, which makes it portable for various processes and also suitable for SoC applications. This ADPLL will be implemented using TSMC’s 0.09 um CMOS technology.

I. INTRODUCTION

The phase-locked loop is one of most widely used circuits for providing clocks in digital designs. Traditionally a PLL was made as an analog building block. Using an analog PLL in a digital noisy system–on-chip (SoC) environment causes complex integrating and interfacing issues. Recent CMOS processes in nanometer scale, offering limited voltage headroom and poor analog extensions, proved to be inadequate for integration of sophisticated analog functions. The switching noise of massive digital circuitry heavily degrades the analog path, and the highly nonlinear C_V characteristic of new MOS devices makes the frequency tuning a really challenging tasks. In addition, the analog PLL is sensitive to process parameters and must, therefore be redesigned for each new technology. Digital Controlled Oscillators (DCO) or clock generators will definitely have lesser performance but are much easier to implement without targeting a specific technology. Basically, DCO dominates the major performances of ADPLL such as power consumption and jitter, and hence is the most important component of such clocking circuits. Since DCO occupies over 50% power consumption of an ADPLL [2], the power consumption of DCO should be reduced further to save overall power dissipation to meet low-power demands in SoC designs.

Recently, different architectural solutions have been proposed to implement the DCO.

If an all digital controlled PLL is made with only active components such as transistors, it will scale nicely with technology. Capacitors and resistors that are used in analog circuits will not scale with the technology changes to the same extent. A PLL designed with standardized digital CMOS components (standard cells), is easy to implement using any CMOS technology, and can, therefore, radically decrease time-to-market for a design. Moreover, if the entire PLL is described in a HDL language, system simulations including the PLL can be performed with a digital HDL simulator.



Fig. 1 General PLL block structure

The critical component for a PLL made with standard cells is the oscillator, which has to be simulated as an analog component to get reliable estimates of its behavior. Simulating an oscillator is, however, much less troublesome than simulating a PLL due to lack of nonlinear feedback loops. The aim for this project is mainly to reduce the complexity in digital PLL design to the complexity of designing the oscillator.

The block structure of a general PLL, shown in Fig. 1, is divided into a phase detector, a loop filter, an oscillator, and a frequency divider. The design methodology used for this digitally controlled PLL is to transform the components used in the analog PLL into the digital domain. This results in a simple, area-effective low-power solution

A. Algorithm

In this section, we will discuss the algorithm of the ADPLL. The conventional ADPLL [3] uses four modes of operation: frequency acquisition, phase acquisition, frequency maintenance and phase maintenance. Each mode is like a "search" algorithm with different adaptive scheme. Phase lock begins with frequency acquisition. When frequency acquisition is complete, the ADPLL enters phase acquisition mode. After phase lock completes, the ADPLL enters both frequency maintenance and phase maintenance. In frequency acquisition mode, in order to find the target frequency, the conventional ADPLL uses a modified binary search algorithm.. The modified binary-search algorithm sweeps the DCO frequency range to match the target frequency. On every change in search direction the frequency gain is reduced by a factor of 2. Comparing the modified binary search with Search technique, the difference is the change of gain value. In new algorithm, the frequency comparator can find the optimized gain value and reduce the searching step by the optimized gain value. So in new searching algorithm, ADPLL does not need to sweep the overall DCO frequency range to match the external frequency.

In phase acquisition mode, our ADPLL aligns thebuffered output (do not need divider circuit) of the DCO to the matched delay reference clock. In new algorithm, we execute the frequency acquisition and phase acquisition at the same time so we use only one mode to finish the frequency acquisition, phase acquisition and frequency/phase maintenance. In our ADPLL algorithm, the operation is just like the digital phase-locked loop (DPLL) but the design of the building block is all digital circuit.

B. Architecture

There are some major building blocks in the proposed ADPLL. They are phase/frequency detector (PDF), gain generation unit, DCO. Fig. 2 shows the block diagram of the proposed ADPLL. A similar architecture is implemented in [4]. The function of each block will be described in the following:

(1) PFD

This is a block that tells whether the DCO frequency is slower or faster as compared to the reference signal. It provides three outputs. First a regular fast or slow signal, next it gives a lock signal, and the third signal is a clear signal which clears the D4 – D7_5 when the fast signal is generated.



Fig. 2 ADPLL Architecture

(2) Gain generation unit

The PFD here is generating two different gain values when the DCO frequency is more than the reference value and when the DCO frequency is lower than the reference clock. In both the cases this gain figure is stored into the gain register and thus further added and subtracted depending upon the value of fast and slow signal .

(3) DCO

DCO is the heart of the ADPLL. It is a ring oscillator and it is constructed by inverters. The frequency control mechanism is through the binary weighted control word and the control word is generated by the DCO register.

(4) DCO Enable Generator:

The DCO enable generator will generate the enable signal and disable signal for digital controlled oscillator. By using this DCO enable generator we can align the first rising edge of external signal and internal signal every two reference cycles. When the enable signal is low, the DCO will be disabled and the disable time is very short.




III. CIRCUIT DESIGN

A. Phase/Frequency Detector

In conventional ADPLL, the frequency comparator accepts the reference clock and the output of DCO output buffer as its inputs. The frequency comparator will generate the Fast signal or the signal Slow. The phase detector also detects the reference clock and the output of the DCO output buffer and generates the Ahead signal or the Behind signal. In our ADPLL, we combine the two function blocks (frequency detect and phase align) and they work in one mode. So our proposed PFD detects the frequency and the phase at the same time. The PFD also provides the information of the gain value without using modified binary search. The proposed PFD was shown in the Fig.3. As shows in the Fig.3, our PFD detects the frequency and phase every two reference cycles so the frequency of the reference clock was divided by two. The positive edge block will generate a pulse signal at rising edge of the input signal. The output of the positive edge block will clear the output of each D Flip-Flop D1-D7_5 at the rising edge of every two references clocks. The ten D Flip-Flops detect the frequency and generate the information of gain value. The D8 1 signal was delayed by two inverters from D8 signal so the D8 signal and D8_1 signal was very closely.

The detected point is at the rising edge of the reference clock, when the ADPLL was locked, the D8 signal was low and the D8_1 signal was high at the detected point. If the D8 signal is already high at the detect point, it means the DCO frequency is faster than the target The difference from[4] is that our PFD is using less flops to generate gain.

B. Gain generation unit

In our proposed circuit the gain is not generated by any binary search technique but it is generated from the PFD output. This gain is then directly fed to the gain register and then according to the fast and the slow signal this gain is added or subtracted from the previous DCO register value and fed to the DCO register. The gain calculation is done as suppose the if the free running frequency of the DCO is 160 MHz where as target frequency is 120MHz .then registers 1-7_5 will be loaded with one and in the next cycle D8 and D8_1 will be loaded further this will generate the clear signal this signal will clear the flops from D4 to D7_5 . and now fast signal will be generated which will decide data will be subtracted from the previous value of the DCO register.

C. Digital Controlled Oscillator

The traditional DCO will be used like all other architectures it will also have a frequency control mechanism along with a frequency generating oscillator. Ring oscillator with a series of inverters is implemented where for coarse tuning a separate set of inverter paths. Where as the fine tuning is done by using a parallel series of tri-state inverters to add the current drive to each inverter stage. All the non used paths are gated in order to reduce power.

IV RESULTS EXPECTED

Since no resistors and capacitors are used this PLL will definitely have a small area and use of clock gating in DCO at the paths not used will make it low power consuming. Expected power consumption will be 0.3 – 1 mW at operating frequency of 100 – 200 MHz.

V CONCLUSION

A low power, high speed ADPLL design is proposed which is also area efficient as compared to its analog counterpart.

REFERENCES

[1] R. B. Staszewski, D. Leipold, K. Muhammad, and P. T. Balsara, All Digital PLL with Ultra Fast Settling, IEEE Trans. Circuits Syst. II, Exp. Briefs, Vol. 54, no. 2, pp. 181 185, Jan. 2007.

[2] J. M. Rabaey, Digital Integrated Circuits A Design Perspective, second ed. Englewood Cliffs, NJ: Prentice-Hall, 2003.

[3] J. Dunning, G. Garcia, J. Lundberg and E. Nuckolls, An All-Digital Phase-Locked Loop with 50-Cycle Lock Time Suitable for High-Performance Microprocessors , IEEIE JSSC, vol. 30, pp. 412-422, Apr. 1995.

[4] Tzu-Chiang Chao and Wei Hwang ,A 1.7mW All Digital Phase-Locked Loop with New Gain Generator and Low Power DCO, IEEE Trans. Circuits Syst., 2006. ISCAS 2006,May 2006.

[5] R. Tonietto, E. Zuffetti, R.Castello , A 3MHz Bandwidth Low Noise RF All Digital PLL with 12ps Resolution Time to Digital Converter, IEEE J. Solid-State Circuits, ESSCIRC 2006 pp. 150 153, Sept. 2006.