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Measuring Quality in Semiconductor IP
By Piyush Sancheti, Atrenta Inc
edadesignline.com (September 29, 2008)
Semiconductor IP reuse can yield a 2x improvement in design productivity for semiconductor companies. However, with these startling productivity gains come integration pain. Why? Semiconductor IP is essentially a black box for the SoC team that comes from various external sources, with varying and often unknown levels of quality and reusability. SoC designers must find a quality metric for semiconductor IP. If not, they may abandon its use.
Most semiconductor IP today is delivered as soft IP - register transfer level (RTL) or configurable generators that produce RTL. IP suppliers do ensure correct functional behavior. Often overlooked in this process is the communication of design intent and implementation feasibility, a task left for the IP consumer to deal with. A poorly designed IP can result in failures at the SoC level with timing, routing congestion, power, clock synchronization, test coverage, etc. Typically these issues will not be uncovered until after a significant engineering effort has been spent on integration of the IP into the SoC and subsequent implementation. The net result is expensive design iterations, project delays and potential silicon failure.
edadesignline.com (September 29, 2008)
Semiconductor IP reuse can yield a 2x improvement in design productivity for semiconductor companies. However, with these startling productivity gains come integration pain. Why? Semiconductor IP is essentially a black box for the SoC team that comes from various external sources, with varying and often unknown levels of quality and reusability. SoC designers must find a quality metric for semiconductor IP. If not, they may abandon its use.
Most semiconductor IP today is delivered as soft IP - register transfer level (RTL) or configurable generators that produce RTL. IP suppliers do ensure correct functional behavior. Often overlooked in this process is the communication of design intent and implementation feasibility, a task left for the IP consumer to deal with. A poorly designed IP can result in failures at the SoC level with timing, routing congestion, power, clock synchronization, test coverage, etc. Typically these issues will not be uncovered until after a significant engineering effort has been spent on integration of the IP into the SoC and subsequent implementation. The net result is expensive design iterations, project delays and potential silicon failure.
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