English
Multicore SoCs change interconnect requirements
Greg Shippen, Freescale Semiconductor
EE Times (10/20/2008 12:01 AM EDT)
The recent appearance of multicore system-on-chip (SoC) devices has rearranged the boundaries among silicon devices, boards and subsystems. This trend has led to significant changes in chip-to-chip and board-to-board interconnect requirements. Are existing standards-based interconnects ready for this transition?
With the introduction of the microprocessor in the 1970s, simple computing systems were constructed on a single board using a discrete processor, memory controller and I/O interface device. Board-level buses connected the devices; when higher performance was desired, multiple boards were assembled together. Backplanes provided communication between cards using a system-level bus.
These board- and system-interconnect protocols were proprietary. Over time, closed protocols gave way to standardized protocols such as Ethernet, PCI Express or RapidIO.
EE Times (10/20/2008 12:01 AM EDT)
The recent appearance of multicore system-on-chip (SoC) devices has rearranged the boundaries among silicon devices, boards and subsystems. This trend has led to significant changes in chip-to-chip and board-to-board interconnect requirements. Are existing standards-based interconnects ready for this transition?
With the introduction of the microprocessor in the 1970s, simple computing systems were constructed on a single board using a discrete processor, memory controller and I/O interface device. Board-level buses connected the devices; when higher performance was desired, multiple boards were assembled together. Backplanes provided communication between cards using a system-level bus.
These board- and system-interconnect protocols were proprietary. Over time, closed protocols gave way to standardized protocols such as Ethernet, PCI Express or RapidIO.
|
E-mail This Article | 
|
|
Printer-Friendly Page |
|
||||||
Related Articles
- Defining standard Debug Interface Socket requirements for OCP-compliant multicore SoCs: Part 2
- Defining standard Debug Interface Socket requirements for OCP-Compliant multicore SoCs: Part 1
- Meeting Increasing Performance Requirements in Embedded Applications with Scalable Multicore Processors
- Meeting IP Requirements of New Auto SoCs
- Method for Booting ARM Based Multi-Core SoCs
New Articles
- Quantum Readiness Considerations for Suppliers and Manufacturers
- A Rad Hard ASIC Design Approach: Triple Modular Redundancy (TMR)
- Early Interactive Short Isolation for Faster SoC Verification
- The Ideal Crypto Coprocessor with Root of Trust to Support Customer Complete Full Chip Evaluation: PUFcc gained SESIP and PSA Certified™ Level 3 RoT Component Certification
- Advanced Packaging and Chiplets Can Be for Everyone
Most Popular
- System Verilog Assertions Simplified
- System Verilog Macro: A Powerful Feature for Design Verification Projects
- UPF Constraint coding for SoC - A Case Study
- Dynamic Memory Allocation and Fragmentation in C and C++
- Enhancing VLSI Design Efficiency: Tackling Congestion and Shorts with Practical Approaches and PnR Tool (ICC2)