English
ICE-IP-338 High-speed XTS-GCM Multi Stream Inline Cipher Engine
Multicore SoCs change interconnect requirements
Greg Shippen, Freescale Semiconductor
EE Times (10/20/2008 12:01 AM EDT)
The recent appearance of multicore system-on-chip (SoC) devices has rearranged the boundaries among silicon devices, boards and subsystems. This trend has led to significant changes in chip-to-chip and board-to-board interconnect requirements. Are existing standards-based interconnects ready for this transition?
With the introduction of the microprocessor in the 1970s, simple computing systems were constructed on a single board using a discrete processor, memory controller and I/O interface device. Board-level buses connected the devices; when higher performance was desired, multiple boards were assembled together. Backplanes provided communication between cards using a system-level bus.
These board- and system-interconnect protocols were proprietary. Over time, closed protocols gave way to standardized protocols such as Ethernet, PCI Express or RapidIO.
EE Times (10/20/2008 12:01 AM EDT)
The recent appearance of multicore system-on-chip (SoC) devices has rearranged the boundaries among silicon devices, boards and subsystems. This trend has led to significant changes in chip-to-chip and board-to-board interconnect requirements. Are existing standards-based interconnects ready for this transition?
With the introduction of the microprocessor in the 1970s, simple computing systems were constructed on a single board using a discrete processor, memory controller and I/O interface device. Board-level buses connected the devices; when higher performance was desired, multiple boards were assembled together. Backplanes provided communication between cards using a system-level bus.
These board- and system-interconnect protocols were proprietary. Over time, closed protocols gave way to standardized protocols such as Ethernet, PCI Express or RapidIO.
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