Squeeze power efficiency out of processor-based designs -- Part one
industrialcontroldesignline.com (November 19, 2008)
Low power consumption is paramount in all types of processor-based embedded systems. Battery-based portable systems obviously require a low-power methodology. But even line-powered systems also benefit from a low-power architecture that eliminates heat and meets power-usage guidelines. In this two-part article, we offer tips and tricks for power optimization and power system design. Part one focuses how to minimize power consumption by adequately using multiple power operating modes. Part two will provide tips for optimizing resources and extending battery life by designing more efficiently.
Processors play a key role in minimizing power consumption and extending battery life. Too often, designers limit their options for minimizing power consumption to little more than using low-power components. In fact, because processors can control the entire system, they in turn offer several ways to reduce and save on power consumption.
Adopting a disciplined thought process that includes gaining a thorough understanding of how the application affects power, identifying power-hungry parts of the design and application, comparing configuration options and writing power-efficient code are keys ways to maximize power efficiency overall.
As a starting point, think of processor power consumption as having two fundamental power components: static and active. Static power is consumed when there is no CPU activity on the digital signal processor (DSP) or microcontroller (MCU). For the most part, static power is determined by semiconductor process technology, processor core and I/O voltages, and device operating temperature. Semiconductor vendors can minimize static power with process-oriented adjustments such as using processes and transistors with low leakage currents and power-optimized design constraints -- the accompanying tradeoff, however, is often lower frequency and thus lower processor performance.
E-mail This Article | Printer-Friendly Page |
|
Related Articles
- Optimizing embedded software for power efficiency: Part 4 - Peripheral and algorithmic optimization
- Optimizing embedded software for power efficiency: Part 3 - Optimizing data flow and memory
- Optimizing embedded software for power efficiency: Part 2 - Minimizing hardware power
- Optimizing embedded software for power efficiency: Part 1 - measuring power
- Improving Efficiency, Output Power with 802.11a Out-Phasing PAs