English
Architecting the OCP uVC verification component
By Mark Litterick, Verilab
edadesignline.com (January 13, 2009)
Architecting effective verification components for something as flexible as the Open Core Protocol requires a detailed understanding not only of the corresponding specification, but also the environments and methodology in which the verification component will be used. This article demonstrates how two key aspects of OCP - profiles and transactions - were adopted as fundamental building blocks for the architecture of a verification component targeted at constrained-random validation of OCP components and systems.
The article uses the Verilab OCP uVC as an example. The Verilab OCP uVC is a mixed language OCP compliant verification component that supports a major subset of Open Core Protocol Specification 2.2. The OCP uVC is implemented using SystemVerilog and e verification languages and is compliant with both the Open Verification Methodology (OVM) and e Reuse Methodology (eRM). The verification component can be used in SystemVerilog only applications without the Specman layer (or license), or it can be used in Specman-based verification environments as a regular eVC.
edadesignline.com (January 13, 2009)
Architecting effective verification components for something as flexible as the Open Core Protocol requires a detailed understanding not only of the corresponding specification, but also the environments and methodology in which the verification component will be used. This article demonstrates how two key aspects of OCP - profiles and transactions - were adopted as fundamental building blocks for the architecture of a verification component targeted at constrained-random validation of OCP components and systems.
The article uses the Verilab OCP uVC as an example. The Verilab OCP uVC is a mixed language OCP compliant verification component that supports a major subset of Open Core Protocol Specification 2.2. The OCP uVC is implemented using SystemVerilog and e verification languages and is compliant with both the Open Verification Methodology (OVM) and e Reuse Methodology (eRM). The verification component can be used in SystemVerilog only applications without the Specman layer (or license), or it can be used in Specman-based verification environments as a regular eVC.
|
E-mail This Article | 
|
|
Printer-Friendly Page |
|
||||||
Related Articles
- OCP 2.2 MVC Accelerates Verification Productivity
- Automated Formal Verification of OCP based IPs using Cadence's OCP VIP library
- OCP VIP: A cost effective and robust qualification process for multimedia and telecom SoC designs
- Verifying Configurable Verification Interfaces Using OCP
- A comprehensive approach for verification of OCP-based SoCs
New Articles
- Quantum Readiness Considerations for Suppliers and Manufacturers
- A Rad Hard ASIC Design Approach: Triple Modular Redundancy (TMR)
- Early Interactive Short Isolation for Faster SoC Verification
- The Ideal Crypto Coprocessor with Root of Trust to Support Customer Complete Full Chip Evaluation: PUFcc gained SESIP and PSA Certified™ Level 3 RoT Component Certification
- Advanced Packaging and Chiplets Can Be for Everyone
Most Popular
- System Verilog Assertions Simplified
- System Verilog Macro: A Powerful Feature for Design Verification Projects
- UPF Constraint coding for SoC - A Case Study
- Dynamic Memory Allocation and Fragmentation in C and C++
- Enhancing VLSI Design Efficiency: Tackling Congestion and Shorts with Practical Approaches and PnR Tool (ICC2)