English
An application modeling & hardware description for network-on-chip benchmarking
By Erno Salminen, Cristian Grecu, Timo D. Hamalainen, and Andre Ivanov
dspdesignline.com (January 14, 2009)
Measuring and comparing performance, cost, and other features of advanced communication architectures for complex multicore/multiprocessor systems on chip is a significant challenge which has hardly been addressed so far.
The NoC Benchmarking Workgroup of OCP-IP presents a modeling concept for applications running on multicore systems and defines an XML format for documenting and distributing network-on-chip benchmarks.
It defines a black-box view of the processing elements that discloses only the computational aspects that are relevant in interacting with the on chip data transport mechanism. The purpose is to lay the groundwork for a standardized NoC benchmark set.
No optimal NoC exists in general case and a brute-force search is impossible due to vast design space. Benchmarking, however, allows identifying the most promising solutions which are then selected for detailed and more time consuming analysis.
This reduces the design time notably once the major characteristics and requirements of the system are known. Furthermore, common point of reference is required for detailed comparison of approaches. Hence, NoC benchmarking aims to answer two basic questions:
1) NoC developer: What gain does my novel feature bring? .
2) System integrator: Which NoC should I choose? How should I configure it?
The model and the corresponding XML description are divided into four main sections:
1) Application defines the workload in terms of computation and communication.
2) Mapping binds the application tasks to the resources.
3) Platform defines the resources and the NoC interconnecting them.
4) Measurement section defines how to perform the evaluation, for example metrics and simulation length.
dspdesignline.com (January 14, 2009)
Measuring and comparing performance, cost, and other features of advanced communication architectures for complex multicore/multiprocessor systems on chip is a significant challenge which has hardly been addressed so far.
The NoC Benchmarking Workgroup of OCP-IP presents a modeling concept for applications running on multicore systems and defines an XML format for documenting and distributing network-on-chip benchmarks.
It defines a black-box view of the processing elements that discloses only the computational aspects that are relevant in interacting with the on chip data transport mechanism. The purpose is to lay the groundwork for a standardized NoC benchmark set.
No optimal NoC exists in general case and a brute-force search is impossible due to vast design space. Benchmarking, however, allows identifying the most promising solutions which are then selected for detailed and more time consuming analysis.
This reduces the design time notably once the major characteristics and requirements of the system are known. Furthermore, common point of reference is required for detailed comparison of approaches. Hence, NoC benchmarking aims to answer two basic questions:
1) NoC developer: What gain does my novel feature bring? .
2) System integrator: Which NoC should I choose? How should I configure it?
The model and the corresponding XML description are divided into four main sections:
1) Application defines the workload in terms of computation and communication.
2) Mapping binds the application tasks to the resources.
3) Platform defines the resources and the NoC interconnecting them.
4) Measurement section defines how to perform the evaluation, for example metrics and simulation length.
|
E-mail This Article | 
|
|
Printer-Friendly Page |
Related Articles
- Why verification matters in network-on-chip (NoC) design
- Extending network-on-chip (NoC) technology to chiplets
- Network-on-chip (NoC) interconnect topologies explained
- SoC design: When is a network-on-chip (NoC) not enough?
- Application Hardware Modeling: Selective modeling for early prediction of subsystem performances through simulation
New Articles
- Quantum Readiness Considerations for Suppliers and Manufacturers
- A Rad Hard ASIC Design Approach: Triple Modular Redundancy (TMR)
- Early Interactive Short Isolation for Faster SoC Verification
- The Ideal Crypto Coprocessor with Root of Trust to Support Customer Complete Full Chip Evaluation: PUFcc gained SESIP and PSA Certified™ Level 3 RoT Component Certification
- Advanced Packaging and Chiplets Can Be for Everyone
Most Popular
- System Verilog Assertions Simplified
- System Verilog Macro: A Powerful Feature for Design Verification Projects
- UPF Constraint coding for SoC - A Case Study
- Dynamic Memory Allocation and Fragmentation in C and C++
- Enhancing VLSI Design Efficiency: Tackling Congestion and Shorts with Practical Approaches and PnR Tool (ICC2)