Leveraging System Models for RTL Functional Verification using Sequential Logic Equivalence Checking (SLEC).
By Anmol Mathur, Calypto Design Systems
edadesignline.com (January 23, 2009)
Design teams commonly use system models for verification. System models have many advantages over register transfer level (RTL) code for verification, notably, because of their ease of development and runtime performance. The ability to leverage the system-level verification to create functionally correct RTL code has challenged many a design team until now. A methodology known as Sequential Logic Equivalence Checking (SLEC) has the unique capability to formally verify RTL implementations against a specification written in C/C++ or System C.
This article will describe the system-level design flow of a commercial graphics processing chip. In this flow, system models have been developed to validate the arithmetic computation of video instructions and then used to verify the RTL implementation using the SLEC methodology.
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