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PCIe catches up in embedded system design
Addition of multicast to Rev. 2 makes PCIe a viable interconnect option in many embedded designs.
By Matt Jones, IDT
videsignline.com (February 07, 2009)
PCIe, the serial interconnect upgrade to the bus-based PCI and PCI-X standards, was defined to provide increased, scalable performance and alleviate the signal-integrity and board-layout issues introduced by the historical widening of the parallel buses.
The need for this upgraded interconnect standard was most acute in demanding desktop and enterprise computing, and storage applications, and this necessity drove the PCI Special Interest Group (PCI-SIG) and component suppliers to tailor the initial specification and system solutions to meet the emergent requirements of these applications.
But, despite the overwhelming momentum of PCIe and its ubiquity in computing and storage applications, adoption in embedded and communications applications has been largely limited.
Historically speaking, the adoption of new interconnect technologies in these applications trails adoption in other markets due to longer design cycles and product lifetimes. Additionally, in the case of the transition to PCIe, the embedded and communications markets have trailed in their transition as PCI and PCI-X, which is predominantly used in the control plane, continued to ably meet system performance needs.
Today, however, next-generation designs and product refreshes naturally gravitate toward PCIe to leverage the rich ecosystem of off-the-shelf processor, peripheral, and switching solutions featuring PCIe as the native interface, but adoption still remains limited as the PCIe specification and the PCIe-based interconnect and switching solutions had to evolve to address the specific needs of these markets.
The PCIe specification defines a tree-based PCIe topology with a single root and multiple leaves that is well-suited for efficient connectivity between a single computing complex and its associated local I/O. This structure--perfect for server and storage applications--does not contemplate or readily lend itself to system interconnectivity in multi-root systems.
By Matt Jones, IDT
videsignline.com (February 07, 2009)
PCIe, the serial interconnect upgrade to the bus-based PCI and PCI-X standards, was defined to provide increased, scalable performance and alleviate the signal-integrity and board-layout issues introduced by the historical widening of the parallel buses.
The need for this upgraded interconnect standard was most acute in demanding desktop and enterprise computing, and storage applications, and this necessity drove the PCI Special Interest Group (PCI-SIG) and component suppliers to tailor the initial specification and system solutions to meet the emergent requirements of these applications.
But, despite the overwhelming momentum of PCIe and its ubiquity in computing and storage applications, adoption in embedded and communications applications has been largely limited.
Historically speaking, the adoption of new interconnect technologies in these applications trails adoption in other markets due to longer design cycles and product lifetimes. Additionally, in the case of the transition to PCIe, the embedded and communications markets have trailed in their transition as PCI and PCI-X, which is predominantly used in the control plane, continued to ably meet system performance needs.
Today, however, next-generation designs and product refreshes naturally gravitate toward PCIe to leverage the rich ecosystem of off-the-shelf processor, peripheral, and switching solutions featuring PCIe as the native interface, but adoption still remains limited as the PCIe specification and the PCIe-based interconnect and switching solutions had to evolve to address the specific needs of these markets.
The PCIe specification defines a tree-based PCIe topology with a single root and multiple leaves that is well-suited for efficient connectivity between a single computing complex and its associated local I/O. This structure--perfect for server and storage applications--does not contemplate or readily lend itself to system interconnectivity in multi-root systems.
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