Advances in SoC and Processor Modeling Methodologies

By Syed Saif Abrar, NXP Semiconductors

Abstract :

Increasing complexities of the programmable components demand newer modeling methodologies. Architects need to evaluate various design constraints in a short time and also generate tools for the new architecture. Although SoC and processor modeling has been around for a long time, newer methodologies are still being put forward to overcome limitations like limited architecture modeling capabilities, slower simulation speeds, little/less validation support, issues with synthesis, etc. The most common approach being followed is to raise the level of abstraction for describing processor architecture. This paper explores some of the exotic solutions in industry-use, like architecture-description-languages (ADL), extensible architectures, rule based approach and model-driven-architecture (MDA). There has been a surge in the modeling activities, with both EDA-vendors and research-community offering newer methodologies. The paper intends to familiarize the reader with the diversity of available solutions, and discuss their pros and cons.

1. Introduction

As embedded systems become ubiquitous and demanding, programmable components (like processor core, coprocessors and memory subsystem) are increasing in their complexities. This requires design-exploration, tool-suite generation, synthesis, test generation, validation, etc as early as possible in the design stage. As Figure 1 shows, processor design entry methodology must support modeling, analysis and refinement of a new or existing processor. Traditional hardware description languages (HDL), such as VHDL and Verilog, do not have sufficient abstraction to describe architectures and explore them at the system level. As a consequence, designers are moving from HDLs to methodologies supporting higher level of abstraction. Alternate methods like ADLs for processor cores, rule based approach for complex digital circuits design and UML & MDA for SoC modeling are getting wide acceptance. This paper presents a brief survey of the latest tools and methodologies which support modeling of processors and SoCs. The intent is to familiarize the reader with the diversity of available solutions, without being an exhaustive reference.


Fig 1. Expectations from processor modeling
 
The organization of the paper is as follows. Section 2 describes the related work. The methodologies discussed in this paper are overviewed in section 3. Sections 4,5,6,7 and 8 provide details, pros & cons and use-case of each methodology. The paper is concluded by section 9.

2. Related Work

For a long time, processor modeling has been receiving attention from a diverse set of communities. A popular approach to processor modeling is the usage of ADLs, that began around 1980s[1]. ADLs have been used for purposes such as retargetable compilation [2], DSP tools [3], SoC design[4 ], etc. ADLs can be classified into four categories based on the nature of the information: structural, behavioral, mixed, and partial. The structural ADLs, e.g. MIMOLA [5], capture the structure in terms of components and their connectivity. The behavioral ADLs, e.g. nML [6], capture the instruction-set behavior. The mixed ADLs, e.g. EXPRESSION [7], capture both structure and behavior. The other category is partial ADL, which can capture specific information about the architecture for the intended task. For example AIDL[8] that aims at validation of the pipeline behaviour, such as dataforwarding and out-of-order completion, of superscalar processors.

3. Latest Processor Modeling Solutions

ArchC[9] is an open-source mixed ADL that generates a processor-simulator supporting multiple abstraction-levels. The simulator can be both instruction-accurate or cycle-accurate with complete pipeline behavior.

LISA[12] is a mixed ADL that can easily model SIMD, MIMD and VLIW architectures, along with complex pipelines and multi-threading. From a single processor description, complete set of development tools including compiler, assembler, linker, debugger, simulator and RTL are generated.
Tensilica Instruction Extension Language (TIE)[17] is a description language for instruction extensions of Tensilica's  Xtensa processors. The base micro-architecture and instruction set of each Xtensa processor are predefined by Tensilica. Users can augment the processor with new instructions that are created to improve the execution efficiency for a particular set of applications.

Bluespec[19] is a rule-based language, which describes computation as a series of atomic state changes. Expressing design as rules simplifies design considerably, increases designer’s efficiency and can be checked by the compiler automatically The Bluespec compiler generates the necessary hardware (muxs and control) without the intervention of the designer and micro-protocols need less or no verification. Finally, the design can be compiled into Verilog RTL, cycle-accurate C-simulation or SystemC-model.

Model Driven Architecture (MDA)[25] aims to develop models independent of the implementation platform, using UML. The essence of MDA is that the creation of executable software architecture should be driven by the formulation of models rather than by manually writing source code.

4. ArchC

ArchC[10] is a mixed description language, where both structural and behavioral descriptions are to be specified. It is based upon SystemC and has been designed at the Computer Systems Laboratory of the Institute of Computing at the University of Campinas (Brazil). ArchC simplifies designing and experimenting with new architectures. It generates simulator from the description. ArchC supports multiple abstractions. Generation of Instruction accurate simulator needs Instruction behavior to be specified with out specifying the pipeline behavior. On the other hand designer can specify detailed description for generation of cycle accurate simulator, that can be specified as a refinement to the less detailed instruction-accurate simulator.

4.1. Advantages & Limitations

ArchC generates a simulator in SystemC, that is getting wide recognition across the modeling-world. It supports integration of GNU-debugger gdb to the generated model. ArchC is readily available at [9] for download along with example descriptions for different popular processors. As an Open Source ADL, ArchC  is expected to get wide acceptance in future. Currently ArchC is still at its initial stages and is to be improved to model complex architectures. At present the output of the tool is limited to simulator (both interpretive and compiled) and assembler [11] generation only.

4.2. Use-cases

ArchC has been used to model RISC processors like MIPS R3000, PowerPC, LEON, SPARC V8 and Micro controllers like 8051 and PIC. These models can be downloaded from the ArchC website [9].

5. LISA

LISA (Language for Instruction Set Architecture) [12] is a mixed modeling language and supports multiple abstractions where instruction accurate or cycle accurate models can be described. It was developed at Aachen University of Technology, Germany. LISA is designed for the formalized description of programmable architectures, their peripherals, and interfaces. A LISA processor description covers the instruction set, the behavioral and the timing model of the underlying hardware, thus providing all essential information for the generation of a complete set of development tools including compiler, assembler, linker and simulator, and RTL.

5.1. Advantages & Limitations

LISATek [13] tool is commercially available from Coware, supporting LISA-2.0 language. The LISA tool-suite is a set of development tools, which is automatically generated from LISA machine descriptions. Providing these tools, a complete software development environment is available which ranges from the assembly source file up to simulation within a comfortable graphical debugger front-end. An important aspect of LISA language is its ability to capture control path explicitly. Explicit modeling of both data path and control is necessary for cycle-accurate simulation. LISATek tool supports Compiled, Interpreted and Just-in-Time Cache Compiled (JIT-CC™) simulator(patented technology from Coware[13]). The LISA language allows to describe hierarchical models which guarantees modularity and reusability. Current limitation of LISA is its inability to handle all the complexities of memory hierarchies.

5.2. Use-cases

Case studies of the Texas Instruments C62x and C54x, the Analog Devices ADSP2101 as well as the ARM7 are presented in [14]. TMS320C62x is a general-purpose fixed-point DSP based on a very long instruction-word (VLIW). ADSP2101 The Analog Devices ADSP2101 is a 16 bit fixed point DSP with 20 bit instruction-word width.

6. XTENSA

XTENSA is an architecture template based description language that assumes a limited architecture template, which is parameterizable for customization. The Tensilica Instruction Extension Language (TIE)[15] is a description language for instruction extensions of Tensilica's Xtensa processors. The base micro architecture and instruction set of each Xtensa processor are predefined by Tensilica. Users can augment the processor with new instructions that are created to improve the execution efficiency for a particular set of applications. It automatically generates software tools tuned to the new instruction-set.

6.1. Advantages & Limitations

Limited architectural flexibility results in efficient tool suits. No micro-architecture (implementation) details are required. Same TIE will work with new base. Automatic configuration of software tools, compiler, instruction-set ,simulator ,debugger etc. Automatic synthesis of efficient hardware compatible with the base processor. TIE is an Extension language, not a language to describe a complete CPU. So description is simple and no expertise is required.

6.2. Use-cases

Because of its limited flexibility the tools and the synthesizable code generated are highly efficient and can be readily implemented on silicon. Xtensa series of processors uses the TIE for additional instruction description. The tool supports profiling where we can identify potential instructions for optimizations.

7. Bluespec

In order to reduce design time in the hardware design cycle more powerful tools for hardware synthesis from high-level descriptions are being introduced. One of these tools is Bluespec.
Bluespec is a strongly typed rule based hardware synthesis language, which makes use of the Term Rewriting System (TRS) [16] to describe computation, as a series of atomic state changes. This rule based methodology is applied in Verilog and SystemC domains both targeting to reduce design time and to generate synthesizable RTL. Bluespec System Verilog (BSV) description can be used to generate synthesizable Verilog RTL description. Bluespec design approach is able to generate RTL that is comparable to handwritten Verilog [17]. Bluespec-SystemC is a C++ library using rule-based approach. Bluespec SystemC also supports multiple abstractions and TLM methodologies existing in SystemC. This also efficiently bridges the synthesis gap between SystemC and synthesizable RTL.

Advantages & Limitations

Bluespec is a hardware description language (HDL), which compiles into TRS. This intermediate TRS[16] description can then be translated through a compiler into either in Verilog RTL or a cycle-accurate C-simulation. Power to express complex static structures and constraints using rules that are checked by the compiler automatically simplifies design considerably and results in simpler and efficient designs. The compiler generates the necessary hardware (muxs and control) with out the intervention of the designer and Micro-protocols need less or no verification. Similarly SystemC models can be written using Bluespec-SystemC and they can be compiled using bsystemc library. Both SystemC and bsystemc modules can coexist in the same SoC framework. Bluespec mainly simplifies complex digital circuit designs and is not specifically aimed at designing processors. But it simplifies modeling complex processors components considerably when compared to RTL languages [17]. Bluespec supports factoring of concepts such as buffered pipelines, completion buffers, and arbiters, into standard libraries. A designer can then instantiate these concepts with application specific data types and connect them arbitrarily. The compiler will then synthesize an optimized design, including automatic generation of control logic.

Use-cases

Bluespec has been used at Sandburst, Bluespec Inc[18]., MIT, and CMU to describe a variety of complex hardware designs. It has also been shown that a simple 5-stage MIPS pipeline and other similarly complex hardware designs can be synthesized using BlueSpec.[17]. IA64 architecture is also being modeled using BSV.

MDA & UML

UML (Unified Modeling Language) and MDA (Model Driven Architecture) are used in software modeling and are standardized by OMG(Object Modeling Group)[19].
Model Driven Architecture (MDA) is being used for SoC modeling recently. The essence of MDA is that the creation of executable software architecture should be driven by the formulation of models rather than by manually writing source code. Source code is generated from the models by a compilation step much as machine code is generated from source code.
The first model that MDA defines is a model with a high level of abstraction that is independent of any implementation technology. This is called a Platform Independent Model (PIM).
In the next step, the PIM is transformed into one or more Platform Specific Models (PSMs). A PSM is tailored to specify the system in terms of the implementation constructs that are available in one specific implementation technology. PSM will only make sense to a developer who has knowledge about the specific platform.

Advantages & Limitations

The designer can introduce new modeling extensions into UML by defining a UML profile. A profile extends the UML metamodel with a set of new modeling elements. In MDA, designer starts by creating a model at a high level of abstraction, which is then transformed into models at progressively lower levels of abstraction until source-code is obtained. This is how models drive the creation of the architecture.

8.2. Use-cases

UML profiles for SystemC[20] can be written where we can generate SystemC models graphically. The UML profile captures both the structural and the behavioral features of the SystemC language, and allows high level modeling of system-on-a-chip with straightforward translation to SystemC code. Exploiting MDA capabilities of defining modeling languages independent of platform and reducible to Platform dependent languages is done by [21].This work is mainly at SoC integration level where application and architecture are modeled at a higher level (PIM). And mapping will be done at this level and generates PSM for specific platform like VHDL, SystemC etc. UML for SoC[22]  and MDA for Soc[23] are being used for system level design and integration.

Conclusions

As the complexity of the processor architecture increases, designers are more and more inclined to use high-level modeling tools and languages. The design process being done earlier using VHDL/Verilog is now taken over by software solutions. This paper highlights different domains which these tools cover. ADL, extensible-architecture, UML-design, etc have been covered  in this paper. Each of these solutions attempts to address a class of processor and has been optimized for that class. It remains to be seen which solution will keep pace with the times and which will be wiped due to competition, practices, issues, etc.

Table 1. Comparison of features in different methodologies

	ArchC	LISA	Tensilica	Bluespec
Proven	SPARC, MIPS, PowerPC, …	ARM, ADSP, TI, VLIW, …	Yes	IA64, MIPS, …
Simulator	SystemC	ISS, SystemC	Yes	Bluesim, bssc
Sw-dev tools	Assembler	Comp/Link/Ldr/Dbg	Comp/Link/Ldr/Dbg	No
Synthesis	No	Yes	Yes	Yes
Verification	No	No	No	Yes
Hand-optimization	Possible	Only HDL	No	?
Learning curve	Small	Medium	Small	High

10. References

[1] Barbacci, M.R.: ‘Instruction set processor specifications (isps): The notation and its applications’, IEEE Trans. Comput., 1981, 30, (1), pp. 24–40

[2] Qin, W., and Malik, S. ‘Architecture description languages for retargetable compilation’, in ‘The compiler design handbook: optimizations machine code generation’ (CRC Press, 2002)

[3] Fauth, A., and Knoll, A.: ‘Automatic generation of DSP program development tools’. Proc. Int. Conf. on Acoustics, Speech and Signal Processing (ICASSP), 1993, pp. 457–460

[4] Tomiyama, H., Halambi, A., Grun, P., Dutt, N., and Nicolau, A.: ‘Architecture description languages for systems-on-chip design’. Proc. Asia Pacific Conf. on Chip Design Language, 1999, pp. 109–116

[5] Leupers, R., and Marwedel, P.: ‘Retargetable code generation based on structural processor descriptions’, Des. Autom. Embedded Syst., 1998, 3, (1), pp. 75–108

[6] Freericks, M.: ‘The nML machine description formalism’. Technical Report TR SM-IMP/DIST/08, TU Berlin, CS Dept., 1993

[7] Halambi, A., Grun, P., Ganesh, V., Khare, A., Dutt, N., and Nicolau, A.: ‘EXPRESSION: A language for architecture exploration through compiler/simulator retargetability’. Proc. Design Automation and Test in Europe (DATE), 1999, pp. 485–490

[8] Morimoto, T., Yamazaki, K., Nakamura, H., Boku, T., and Nakazawa, K.: ‘Superscalar processor design with hardware description language aidl’. Proc. Asia Pacific Conf. on Hardware Description Languages (APCHDL), 1994

[9] http://www.archc.org

[10] http://mesh.dl.sourceforge.net/sourceforge/archc/ac_lrm-v1.5.pdf

[11] Extending the ArchC Language for Automatic Generation of Assemblers Alexandro Baldassin, Paulo Centoducatte and Sandro Rigo In Proceedings of the 17th International Symposium on Computer Architecture and High Performance Computing (SBAC05), pp. 60-67

[12]V. Zivojnovic and S. Pees and H. Meyr. LISA - machine description language and generic machine model for HW/SW co-design. In IEEE Workshop on VLSI Signal Processing, pages 127–136, 1996.

[13] LISATek Product Line. CoWare,  http://www.coware.com.

[14] A Survey on Modeling issues using the Machine Description Language LISA Andreas Hoffmann, Achim Nohl, Gunnar Braun and Heinrich Meyr  Integrated Signal Processing Systems, RWTH Aachen

[15] Gonzalez, R.E. ‘Xtensa: a configurable and extensible processor’, Micro, IEEE Volume 20,  Issue 2,  March-April 2000 Page(s):60 - 70

[16] Arvind and X. Shen, Using Term Rewriting Systems to Design and Verify Processors,IEEE, Micro Special Issue on Modelling and Validation of Micro-processors Vol. 19(3): pp. 36-46, 1999.

[17] N. Dave, Designing A Reorder Buffer in Bluespec, presented at ACM/IEEE International Conference on Formal Methods and Models for Codesign (MEMOCODE),2004.

[18] Augustsson,L., Schwarz,J., and Nikhil, R. S. Bluespec Language Definition, 2001. Sandburst Corp

[19] www.omg.org/mda

[20] A SoC Design Methodology Involving a UML 2.0 Profile for SystemC E. Riccobene1, P. Scandurra1, A. Rosti, S. Bocchio, DATE-2005

[21]Improving SoC Design Flow by means of MDA and UML Profiles Elvinia Riccobene, Alberto Rosti, Patrizia Scandurra

[22] http://jerry.c-lab.de/uml-soc/toc.html DAC Workshop On UML for SoC Design

[23] MDA for SoC Embedded Systems Design, Intensive Signal Processing Experiment_Pierre Boulet, Jean-Luc Dekeyser, C_edric Dumoulin, Philippe Marquet

[28] UML 2.0 Profile for Embedded System Design Petri Kukkala1, Jouni Riihimäki1, Marko Hännikäinen1, Timo D. Hämäläinen1, and Klaus Kronlöf2 DATE’05

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