Simulating Trade-offs in W-CDMA/EDGE Receiver Front Ends

By Kal Kalbasi, Communication Systems Design
January 18, 2002 (5:24 p.m. EST)

Building 2.5/3G mobile phones may seem like an exciting venture. But, once you dive into the designs, they are an RF and mixed-signal nightmare. These mobiles must support high-speed Internet access, but must also pack the capabilities to support a host of RF front ends. In many cases, this means that designers must engineer the RF front end to handle wideband CDMA (W-CDMA) signals as well as other air interfaces such as Enhanced Data Rate for GSM Evolution (EDGE).

One key headache during the development of dual-mode W-CDMA/EDGE design lies in receiver design. A host of advanced architectures, such as direct conversion and digital IF, are being pitched to replace the superheterodyne structures in the receive chain. But to make the shift to these new technologies, especially digital IF, designers must employ a new set of simulation techniques/approaches. Let's explore how simulation can be handled in a digital IF architecture and the impact these sim ulations have on estimating receiver performance.

The architectures

To analyze the performance trade-offs encountered in building dual-mode W-CDMA/EDGE receivers, let's first look at the typical receiver architectures designers can choose from when building these mobile phone designs. Overall, the three most common architectures for mobile phone RF receivers are the superheterodyne, the direct conversion, and digital signal processor (DSP)-based digital IF.

Under the commonly used superheterodyne architecture, out-of-band signals are reduced by a bandpass filter placed immediately after the antenna, followed by a low-noise amplifier (LNA), and a mixer that converts the signal to a first IF in the range of 100 to 200 MHz. After the mixer, one or more stages of filters and amplifiers are used for analog channel filtering. The signal is then amplified and downconverted to baseband for demodulation.

The direct-conversion scheme also includes an RF bandpass filter, LNA, and mixer. The mix er, however, converts directly to baseband, which requires an accurate quadrature at the local oscillator (LO) frequency (same as RF). Other design challenges include dealing with the DC signals generated by imbalances in the mixer, which can be difficult to filter.

The last approach is the DSP-based digital IF approach. The advantage of this method is that channel filtering can be programmable, resulting in a single radio architecture that will adapt to multiple formats. The full bandwidth of the signal still exists after the first mixer, which must be captured by an analog-to-digital converter (ADC) that commonly employs a bandpass sigma-delta converter.

To better illustrate the digital IF method, let's simulate the performance of this design in a mobile phone supporting both EDGE and W-CDMA. In this method, A/D conversion is followed by three main blocks: I/Q down-converter, filter, and demodulator. The design challenge lies in the seemingly simple quadrature and filter operations, since IF proce ssing must extract the desired signal from a wideband input. In our example, the narrowband signal is EDGE or GSM and the wideband signal is W-CDMA.

The input bandwidth of the IF signal is 5 MHz in W-CDMA systems, complying with the 3G Partnership Project (3GPP) specifications. The sampling rate should be chosen such that it satisfies the baseband processing for this wideband signal. The greatest challenge is the extraction of narrowband (EDGE or GSM) from the wideband signal, which must perform properly in the presence of spurious, image, and blocker signals.

Channel select filtering

Based on a proposed architecture, 3GPP and EDGE input signals arrive at an IF signal at 69.12 MHz, which is subsampled at 30.72 MHz (see Figure 1).¹ In general, subsampling follows the relationship Fs = (4/n)FIF with n = 1,3,5,7,9,.. (n = 9 in our example). Subsampling with a rate less than twice the highest frequency allows a simplification of the digital I/Q mixing, since the sine and cosi ne signals representing the complex phasor degenerate to two simple sequences of [1 0 -1 0 ...] and [0 1 0 -1...]. In addition, the 30.72-MHz subsampling rate is equal to 8 times the chip rate of 3GPP signal, that is, 8 x 3.84 = 31.72 MHz.

Click here for Figure 1

Figure 1: Diagrams of a digital IF architecture for a dual-mode W-CDMA/EDGE mobile phone. Figure 1a represents a W-CDMA architecture. Figure 1b represents and EDGE architecture.

Using this approach, the sampled A/D signal is applied to a digital mixer that uses the above sequences. Note that these sequences are effectively cosine and sine multipliers, which reduce the computation requirements. Down-sample decimation by two effectively removes the zero multipliers and brings the sampling rate Fs down to 15.36 MHz. For the wideband case, the last filter is a raised cosine filter for pulse shaping based on the 3GPP standard, with a roll-off rate of 0.22 and attenuation starting at --40 dBc.

The response of this raised cosine filter for various word lengths is shown in Figure 2. It is clear that out-of-band attenuation and droop degrade with fewer bits. The fixed point, RTL or the hardware description language (HDL) representation of this filter with a specifiable bit width can be co-simulated with the RF and baseband portions of the design to assess the distortion it introduces. The results of the co-simulation can then be used to select the minimum (optimum) word length.

Click Here for Figure 2

Figure 2: Frequency response of 3GPP pulse shaping filter for different word lengths.

Under the EDGE spec, the digital IF receiver section extracts the required 200-kHz bandwidth from the 5-MHz received signal. Similar to 3GPP implementation, this starts with multiplication using a periodic sequence of 1s and 0s, then down-sampling by two. This result is followed by a cascade integrator comb (CIC) filter and, finally, by a compensation filter. The up- and down-sampling is adjusted in the compensation filter stage to obtain an output at one sample per symbol, or 270.88 kHz, the symbol rate for

EDGE and GSM

The CIC filter is a highly efficient multiplier-free filter for attenuation of aliasing components.² The frequency response of the CIC filter can be expressed in closed form where N is the order of the filter and R is the down-sampling rate:

In our example, we use N = 5 and R = 32 for the EDGE IF stage. For high values of R, this expression approximates the multiplication of 2N sinc functions, resulting in very low sidebands and deep nulls.

The compensation filter, typically a FIR filter, is simulated with 32, 16, 14, 12, 10, 8, and 6 b to assess the distortions introduced. This filter is a lowpass windowed (Hamming) filter. Here, similar to a pulse-shaping filter of 3GPP, the overall performance is determined by the numb er of bits chosen. The choice of any of these representations requires the designer to do a trade-off analysis in order to come up with the most economical solution (fewer filter taps implies cheaper filter, smaller foot print, and less processing), without jeopardizing the performance of the phone.

Receiver errors

In order to determine the performance margins of the receiver design, the error boundaries should be established through simulation. These results are then augmented by the addition of “real world” margins, which are obtained by prototyping and testing in the design-verification stage. Receiver error sources may stem from many factors, including:

• Synthesizer phase noise

• I/Q demodulator

• Origin offset

• Frequency offset

• Fixed-point implementation

• ADC

Although the list shows that the source of these errors could be coming from the RF, baseband, or analog portion, this article will focus on distortions due to fixed-poi nt effects.

Standard performance verification tests have, in various forms, been incorporated into most digital communication standards. 3GPP and EDGE both have procedures and specifications for the in-channel and off-channel tests.

One of the key specifications for a receiver is sensitivity, which is generally specified at a particular bit error rate (BER). Sensitivity is defined as the median level of the received signal that produces a specified BER when the signal is modulated with a specified pseudorandom binary sequence (PRBS) of data. For our dual mode example, Table 1 summarizes the relevant specifications for EDGE and 3GPP formats.

 

 

 

 

 

 

TABLE 1: Relevant EDGE and 3GPP Specifications
EDGE	3GPP
Channel spacing: 200 kHz	Channel Spacing: 5 MHz
Symbol rate: 270.83 kbps	Transmission chip rate: 3.84 Mchips/s
Receiver sensitivity: --102 dBm	Receiver sensitivity: --121 dBm
Out-of-band CW blocker above desired signal: 76 dB	Adjacent channel selectivity at 5 MHz: ≤63 dB

BER vs. EVM

When performing receiver measurements, most designers will turn to measuring BER performance. While this measurement is very important, BER suffers from some limitations and therefore should be avoided if there is an alternative.

The first limitation is a considerable simulation time required to make this measurement with confidence, especially for systems that require high transmission accuracy. The receiver sensitivities of -102 dBm (EDGE) and -121 dBm (3GPP) may be intensive in the use of computational resources.

Another problem is that BER provides limited diagnosis value. When the value exceeds the threshold, it does not give any clues regarding the probable cause.

Error vector magnitude (EVM) represents the difference between the measured and expected carrier magnitude and phase at a point in time, and the expected magnitude and phase at that same point in time. EVM is generally a transmitter measurement. In recent years, use of EVM as a receiver metric has grown. For exa mple EVM is a valid measurement for pre-detection waveforms, prior to equalization. The use of EVM in these cases is particularly useful when a model or prototype for the equalizer is not available. In the dual-mode handset designs, quantifying the distortions is extremely valuable, even though they may be removed in blocks that follow the IF stage. In these cases, the absolute value of EVM is less important than the trend it manifests.

Simulations

Adjacent channel interferers are typically large, undesired signals from neighboring cells. Blockers are also undesired signals, which may be from within the same cell, offset by two channels. Through simulation, designers want to test channel performance in the presence of adjacent channel and blocker interference. The EDGE specification makes the distinction between blockers and adjacent channel interferers, because the worst case undesired signals are referenced to different desired signal levels.

Using pre-existing simulation setups for adja cent channel and blocking scenarios for 3GPP and EDGE in an existing design and verification environment³, a designer can quickly employ EVM measurement techniques to quantify distortions caused by the digital IF section. In each case, the output of the digital IF is compared to the reference waveform, and the EVM value is computed.

Since one of the objectives of the simulation is to gauge the impact of fixed-point distortions, different fixed-point designs (as well as RTL or HDL code that represents those designs) can be included in the simulation of the digital IF section. Designers must then gauge the resulting value of EVM. The power of the interfering adjacent channel or blocker signal will also be swept to determine the channel selectivity performance of the digital IF.

How it's handled

The simulation of a 3GPP design includes a fixed-rate uplink source with a 12.2-kbps data traffic channel and long scrambling code. The control channels are made inactive for this test sou rce. The source data is then pulse-shaped using a raised cosine filter, modulated, and up-converted to a frequency of 1.9 GHz.

The RF signal is then split, with one signal used as the reference for the EVM measurement. The other is combined with the adjacent channel signal at 5-MHz offset, downconverted to an IF frequency of 69.12 MHz, subsampled at 30.72 MHz with an ideal ADC, and used as the input into the digital IF section.

In EDGE designs, the setup includes a random bit generator driving the EDGE modulator, which includes 8-level phase shift key (8PSK) mapping, 3Π/8 rotation, and pulse shaping with a linearized Gaussian filter.

The signal is then up-converted to a 1.9-GHz RF carrier and used as the waveform transmitted into the propagation channel. After reception, this signal is downconverted and subsampled at 30.72 MHz, using an ideal ADC, and then employed to drive the digital IF section.

Results, analysis

In the narrowband system (EDGE signal), after A/D conversion , the ratio of sampling to signal bandwidth is quite high. In our example, this ratio is 30.72 MHz/200 kHz, which is greater than 153. This means that the sampled signal could include 153 channels. The challenge is then to extract one channel signal by a series of high decimations, without being distorted by aliasing with adjacent channels or blocker signals.

Figure 3 shows the results of simulation in the presence of a CW blocker at the same power level as the desired signal. The figure includes four spectrum plots at the 69.12-MHz IF, after digital mixing, before and after CIC filtering (left to right).

Click here for Figure 3

Figure 3: Waveform and spectrum of EDGE signal at different stages with weak blocker power.

Simulations were run on the same signals but with blocker power 50 dB above the desired signal. In this case, the distortion in waveforms as well as strong aliasing is evident. To s ee the effect of the CIC filter in attenuating the effect of blockers and out-of-band interference, a superposition of the signal-plus-blocker spectrum and the filtered CIC is shown in Figure 4.

Click here for Figure 4

Figure 4: EVM vs. adjacent channel power at 5 and 10 MHz offsets.

Having built confidence in the performance of the channel selection filtering, designers now want to assess the impact of bit imprecision on the signal quality. A simulation was run to determine the EDGE EVM results for different word lengths representing the compensation filter design as a function of adjacent channel power above desired signal.

The results show a mild degradation of EVM for finite word lengths less than 12 and 10 b and a big degradation for wordlength less than 8 b. This points out to the shortest word length for implementation in the digital IF section. Note that EVM results shown are intermediate (pre-detection), and therefore the absolute value of EVM is not as significant since EVM degradation goes up as adjacent channel power increases.

In the case of 3GPP, the EVM simulations are longer since the number of bits (chips) to be processed is much higher. To see the impact of adjacent channel power for 5- and 10-MHz offset, designers can sweep the interfering signal power and record EVM. The results show the progression of distortion measured by EVM.

What's in store

Increasing use of digital IF and direct conversion architectures are trends in the design of multi-mode phones. For digital IF designs, simulation of RF, analog, and baseband signals is a key part of the design process, along with a trade-off study of different channel selection filtering. A mixed-signal simulation platform that provides 3G signal sources, measurements, and verification setups and that integrates floating-point, fixed-point, and HDL co-simulation is invaluable in shortening the upfront design time.

T o achieve faster simulations, EVM can be utilized as an alternative to BER for receiver front-end measurement. In the example above EVM simulations were used to indicate the minimum number of bits for representation of filters in digital IF section using a receiver simulation that included the presence of adjacent channel and blocker interferers.

About the Author

Kal. Kalbasi is a communications application specialist at Agilent's EEsof EDA division. He holds a Ph.D. in electrical engineering from University of Kansas and has more than 12 years of experience in RF and communication systems. He can be reached at kal_kalbasi@agilent.com.

References

1. Jian, M., Yung, W.H., and Songrong, B., “An Efficient IF Architecture for Dual-Mode GSM/W-CDMA Receiver of a Software Radio,” IEEE International Workshop on Mobile Multimedia Communications, San Diego, CA, November 1999.

2. Hogenauer, E.B., “An economical class of digital filters for decimation and interpolation,” IEEE Transactions on Acoustics, Speech and Signal Processing, ASSP-29(2):155-162, 1981.

3. Advanced Design System, Agilent EEsof EDA.