SoC test requirements debated

SoC test requirements debated
By Nicolas Mokhoff, EE Times
November 2, 2001 (4:45 p.m. EST)
URL: http://www.eetimes.com/story/OEG20011102S0104

BALTIMORE — The prevalence and escalating cost of system-on-chip (SoC) designs are forcing a reexamination of existing approaches to design and test, according to EDA and test industry executives at a panel session during this week's International Test Conference.

"Today, there is a believe that design-for-test [DFT] technology and tools will help solve increasingly high complexity and cost of SoC testing," said panel moderator Bozena Kaminska, senior vice president and chief technical officer of Fluence Technology Inc. (Beaverton, Ore). "Several ATE [automatic test equipment] vendors are researching and introducing a new class of structural testers, often called DFT testers. EDA companies are facing the same dilemma from a software point of view."

Kaminska challenged panel participants to come up with the perfect SoC test environment.

"Just five years ago most users tested chips one at a time, tested each type on a different machine , and tested digital, mixed-signal, RF and memory separately," said Roger W. Blethen, president and chief executive officer of LTX Corp. (Westwood, Mass.). "Today almost every tester company makes multiple test platforms, each with a different operating system, its own system hardware, and incompatible applications solutions. With the emergence of SoC technology, now is the ideal time to address this situation."

Blethen offered a more efficient approach: use one scalable test platform that enables customers to match their equipment and its cost to the complexity of the chips being tested. He said that the test industry needs two different types of testers: a high-efficiency tester for memories, and a scalable IC tester for everything else.

Multisite test capability is another core requirement for controlling SoC test costs, according to Blethen. "In memory testing, it's common to test 128 chips at a time, with fully integrated test heads and handlers built for parallel memory testing. This test strat egy developed because people saw that parallel testing and standardization would pay off. The system-on-a-chip industry is just beginning to move in a similar direction."

Another item that would impact both time-to-market and the cost of test is the ability to encapsulate test intellectual property (IP) for reuse in subsequent test program development efforts. Reusability of "test methods" in an object-oriented environment will allow an engineer to develop SoC test programs more quickly, knowing that the method being reused has already been optimized for test time and measurement accuracy, Blethen said.

Make or break proposition

New classes of SoCs will present unique technical and economic challenges, according to John Harris, manager of worldwide test engineering at IBM Microelectronics (Burlington, Vt.). "While historically the focus and importance placed on DFT has varied greatly across the industry, with these new types of SoCs, DFT will be a make or break proposition for market s uccess," Harris said. The interdependency of design, EDA tools and test engineering will be stronger than ever, and comprehensive technical and economic analysis of the DFT and test strategy as part of the whole design process will become paramount, he said.

"The problems presented by complex SoCs cannot be left for the ATE companies and test engineers to solve," Harris said. The onus is on the design community to collaborate with EDA tool developers and test engineers to develop the tools and methods that will enable cost-effective manufacturing and test to develop to support the timely launch of SoC products. "If the right choices are not made at the design level, it will be largely impossible to achieve acceptable test coverage and affordable test costs," Harris said.

But the economic challenges of SoC testing will outweigh the technical challenges, Harris said. "Because of conflicting test methodologies and requirements, the test cost for an SoC will greatly exceed the sum of the test cost for s tandalone components making up the SoC function," he said. The dilemma is that SoC test costs are not scaling at the same rate as the cost per SoC transistor. This means that test will escalate as a percentage of total packaged die cost, and the cost of test will become an economic barrier to successful SoC implementation, Harris said.

Tom Newsom, vice president and general manager of the SoC business unit at Agilent Technologies (Palo Alto, Calif.), said that significant investment in research for high-end digital, analog, and RF DFT is under way at Agilent and elsewhere. "The challenge for ATE and design methodology companies is to create a portfolio of test tools, automate the tasks of IP insertion and test development, and have cost-effective test hardware that is up to the SoC testing task at hand, regardless of the device type," he said.

Lori Watrous-deVersterre, general manager for the DFT division of Mentor Graphics Corp. (Wilsonville, Ore.), said costs are directly related to the widening g aps between the design and manufacture of electronic components. He identified them as: