Aeonic Generate Digital PLL for multi-instance, core logic clocking
Code coverage convergence in configurable IP
By P. Venkata Giri Kumar, Nivin Ninan George, Sarannya K, Sriram Balasubramanian, Srikanth Vadanaparthi from Synopsys
Abstract:
Code coverage plays an important role in verification. It is essential to meet the target numbers for the code coverage metrics at the end of functional verification. The verification of a configurable IP focuses on verifying the RTL for multiple configurations. The RTL varies with configurations and hence achieving the targeted code coverage for multiple configurations is a verification challenge. The challenge lies in reducing the additional verification cycles to achieve the code coverage goals.
I. Introduction
Code coverage is an essential metric for completion of the verification of a SoC or an IP. The code coverage report helps you identify verification loopholes by analyzing the uncovered coverage metrics in the report. The target coverage numbers are defined for all the code coverage metrics (Line, Toggle, Condition and FSM). Additional verification cycles are required if the code coverage target metrics are not met. It is required to meet 100 percent coverage goals but it does not mean that verification is complete. However, it is an important metric for the measure of the verification. Code coverage metrics must be used in conjunction with other metrics such as functional coverage, assertion coverage, and formal equivalence checkers [1] to measure verification completion.
In general, verification is a two-dimensional problem. The testbench development, coverage convergence (functional and code) are the two dimensions of the verification. The configurable IP provides third dimension to the IP verification namely Multiple Configurations. Verifying the configurable IP across multiple configurations is a challenging task and challenge lies in both the dimensions. Achieving code coverage goals for multiple configurations requires special attention as it might impact the verification schedule if not addressed properly.
E-mail This Article | Printer-Friendly Page |
|
Synopsys, Inc. Hot IP
Related Articles
- Building more secure embedded software with code coverage analysis
- System Verilog configurable coverage model in an OVM setup - concept of reusability
- Improve functional verification quality with mutation-based code coverage
- Code coverage techniques -- a hands-on view
- Code Coverage is Crucial in the IP Qualification Process
New Articles
- Quantum Readiness Considerations for Suppliers and Manufacturers
- A Rad Hard ASIC Design Approach: Triple Modular Redundancy (TMR)
- Early Interactive Short Isolation for Faster SoC Verification
- The Ideal Crypto Coprocessor with Root of Trust to Support Customer Complete Full Chip Evaluation: PUFcc gained SESIP and PSA Certified™ Level 3 RoT Component Certification
- Advanced Packaging and Chiplets Can Be for Everyone
Most Popular
- System Verilog Macro: A Powerful Feature for Design Verification Projects
- System Verilog Assertions Simplified
- Smart Tracking of SoC Verification Progress Using Synopsys' Hierarchical Verification Plan (HVP)
- Dynamic Memory Allocation and Fragmentation in C and C++
- Synthesis Methodology & Netlist Qualification