Fractional-N Integer LC DESKEW PLLs in FDSOI FDX (GF22FDX SS28FDS ST28FD-SOI 22FDX 28FDS)
How throughput enhancements dramatically boost 802.11n MAC efficiency--Part II
Probir Sarkar, ARM
EETimes (8/18/2010 12:05 PM EDT)
Overview of MAC Improvements
The primary method used to improve the MAC performance is to amortize the high cost of medium access over a larger number of data frames. First, 802.11n incorporates the mechanisms introduced in 802.11e, a prior amendment to the standard. Though these mechanisms were devised to provide differentiated QoS to MAC users, they also help amortize some of the MAC overheads. It introduced the concept of a Transmit Opportunity (TxOP), whereby a station that acquires the medium, does so for a bounded time period (as opposed to a single frame-ack sequence in the original DCF.) Thus the DIFS wait and backoff countdown steps are required only once in every TxOP duration. Another scheme introduced is the Block Acknowledgement (BA.) Instead of each frame being individually acknowledged, a set of frames may be acknowledged using a BA response. This amortizes the response overhead, over a larger number of data frames. These improvements are shown in the first two rows of Figure (3).
![]() |
E-mail This Article | ![]() |
![]() |
Printer-Friendly Page |
|
Arm Ltd Hot IP
Related Articles
- How throughput enhancements dramatically boost 802.11n MAC efficiency--Part I
- New Power Management IP Solution Can Dramatically Increase SoC Energy Efficiency
- COMSIS 802.11n: an IP to Reuse - a flexible platform for Design
- How High-Level Synthesis Can Raise the Efficiency of Design Reuse
- Turbo encoders boost efficiency of a femtocell's DSP
New Articles
- How NoC architecture solves MCU design challenges
- Automating Hardware-Software Consistency in Complex SoCs
- Beyond Limits: Unleashing the 10.7 Gbps LPDDR5X Subsystem
- How to Design Secure SoCs: Essential Security Features for Digital Designers
- System level on-chip monitoring and analytics with Tessent Embedded Analytics
Most Popular
- System Verilog Assertions Simplified
- Synthesis Methodology & Netlist Qualification
- Design Rule Checks (DRC) - A Practical View for 28nm Technology
- Enhancing VLSI Design Efficiency: Tackling Congestion and Shorts with Practical Approaches and PnR Tool (ICC2)
- UPF Constraint coding for SoC - A Case Study