Product How-To: Interoperability comes to EDA
Paul Double, founder and CEO of EDA Solutions
EETimes (10/3/2010 11:27 PM EDT)
Engineers often need to move between Tanner and Mentor Graphics EDA tool sets several times in the design flow. Paul Double, founder and CEO of EDA Solutions, explains how Tanner’s External Verification Interface (EVI) maintains the integrity of the data and how companies can operate more efficiently while keeping tool costs down.
It is common for IC designers to deal with a heterogeneous or multi-tool flow, moving between tools for compelling business reasons. Even though most designs require only a fraction of the functionality and expense of a Mentor Graphics tool suite, some companies purchase full Mentor Graphics tool seats for occasional, large, or complex designs. Many foundries consider Calibre the gold standard for physical verification for full chip sign-off, so designers may obtain Calibre licenses and use Tanner Tools for layout and schematic entry. There is also the learning curve - designers in small companies need easy-to-use, affordable, PC-based tools they can learn quickly for most of their work, while still needing Mentor Graphics tools for complex applications and foundry standards.
However, the back-and-forth movement of files in a multi-tool flow is inefficient and potentially risky. As designers work around binary incompatibilities and move text files from one system to another, this flow broadens the potential for error and introduces several potential problems. One wrong move during the export/import step could result in the use of the wrong file at best, or at worst, in loss or corruption of data. Interoperability among EDA tools removes the manual step and minimizes this risk.
E-mail This Article | Printer-Friendly Page |
Related Articles
- Resolution of Interoperability challenges in Automatic Test Point insertion across different EDA vendors
- FPGA constraints for the modern world: Product how-to
- Product How-to: Fully utilize TSMC’s 28HPC process
- Improve FPGA communications interface clock jitters with external PLLs
- Product how-to: Reliable SoC bus architecture improves performance