Embedded Systems: Programmable Logic -> Adaptive tech extends Moore's Law

Microprocessor and DSP vendors are now hell-bent to use Moore's Law (Gordon Moore's 1965 prediction that the number of transistors that can fit on a chip will double every 18 months) to ramp up their megahertz ratings or embedded multiple processors on the same die as a way to turbocharge their performance. But megahertz does not measure work done, and C programmers have yet to be able to effectively program more than two or three processors in parallel. Years of practice show that attempting to program multiple parallel processors is an exceedingly troublesome job.

The traditional microprocessor and DSP are effectively hitting the proverbial wall. Large amounts of chip overhead and C programming issues pose in herent limitations for conventional microprocessor and DSP architectures. Effort to improving microprocessor performance via architectural changes has waned because traditional chip designers are limited as to how to add gates efficiently in those architectures.

This efficiency gap can be eliminated by opting for adaptive computing machine technology, which can be regarded as bringing a new dimension to Moore's Law-in effect, a time machine dimension. Adaptive computing machine (ACM) technology allows the system designer to change or adapt a processor chip's architecture blazingly fast and on the fly. In other words, he or she can redesign the chip's architecture and constantly recustomize the associated gates over and over to run virtually any number of different algorithms directly in hardware.

ACM technology eliminates the classic efficiency gap. Since the ACM u ses a higher percentage of all of the chip's gates, it allows an engineer to utilize more gates and hands the designer the high levels of computing performance forecast by Moore's Law further out in time. Instead of waiting 18 or 36 months for a larger die, the designer can utilize that number of "efficient" gates today. Adaptive computing can be viewed as a time machine that permits the designer to opt for the higher performance of the future according to Moore's Law and have it now for today's performance-intense applications.

Computational power efficiency (CPE) is a new way to think about efficiency and cost savings. Generally speaking, CPE is defined as the ratio of the number of gates actually used to solve a given problem divided by the total number of clock cycles taken.

The CPE of a typical DSP chip is about 10 percent. This means that typically only 10 percent of the gates on a DSP are used to perform real work at any given time, so only a small portion of the processor is actuall y working to solve a given problem or algorithm. The remaining portion is overhead necessary to keep operational that small piece of the processor. Although the CPE number is low, a DSP chip has the advantage of being software programmable with all its time-to-market advantages.

The CPE number for an ASIC, on the other hand, averages about 25 percent, a two and a half-fold advantage over the DSP solution. These gains, which can be seen as increased performance or reduced power dissipation or both, come at the expense of flexibility. Any changes not envisioned during the design cycle of the ASIC result in a respin of the entire ASIC.

Adaptive computing exhibits a CPE of about 60 percent, an additional 2.5 times gain over the ASIC device. ACM devices also have the advantage of being software programmable or, more precisely, algorithm programmable. This technology allows an algorithm to be run on the most efficient hardware for the minimum amount of time required.

A key point is that t he CPE metric is independent of process technology. An ACM-based processor will always be more efficient over a DSP or ASIC solution at the same process geometry.

As wireless technology moves beyond second and into third and fourth generations, features will be needed that are beyond basic voice and messaging functions in the current batch of mobile products. The ASIC-DSP combination isn't a major contributor in that regard because it takes nine months of engineering and lots of effort and cost to design in only one or two new functions a generation.

Adaptive computing technology helps designers overcome design barriers created by emerging wireless standards.

Adaptive computing also lets the designer dream up almost any feature and have that functionality downloaded to the handset.