SoC: Codesign and Test -> Verification ensures reuse really used

Designers' attempts to cope with this growing drain on their project schedules and resources have often focused on the use of new languages and tools. Those efforts have proved only partially effective. Languages and tools play an important role, but a largely secondary one, in the functional-verification proc ess. The real key to developing a more efficient approach to system-level functional verification for system-on-chip (SoC)-based embedded systems lies in a new methodology. It must be highly flexible and able to accommodate all project participants while minimizing complexity. Most important, it must maximize code and component reuse to successfully accelerate this crucial step in the development cycle.

Although the term "reuse" has often been used in discussions of software development productivity, its definition has become confused and unclear. Certainly, a functional-verification philosophy based on the reuse of code and components can significantly reduce testbench development time and optimize designer productivity. But what specific characteristics of a functional-verification methodology maximize reuse? And how does a design team implement such an approach?

The first step toward constructing a verification test environment that is reusable and extensible is to build it around object-o riented design techniques. Such a data-centric approach should focus on defining highly detailed and accurate descriptions of the data types that are to be found on all the interfaces in a system. For example, the Ethernet interface commonly used in many systems employs an Ethernet packet, and a universal serial bus (USB) interface employs a USB transaction. By tying those specific data types to their respective interfaces and defining them thoroughly and effectively, the designer has taken the first step toward building reusable code for verification purposes.

With this data-centric description of the interfaces in a system, the designer can add functionality that will insert the data into the system under test to perform the verification test or extract data from the system under test to check test results. Once those stimulus-injection and results-extraction functions are written, they can be integrated with the object-oriented data type and encapsulated in larger data types that can be strung tog ether into sequences. Under such a scenario, for example, Ethernet packets can be linked together, controlling the interpacket gap and thereby what bandwidth is used on the Ethernet.

A second key requirement to a reuse methodology is the application of strict code hygiene. To maximize reusability, the software that comprises the design verification environment must be structured in a rigorous manner using established software design concepts-a highly modular software design is crucial. For example, instead of writing a single monolithic file to implement a test, designers should build a separate module that describes how to introduce the stimulus to the device under test, a second one that checks the results and a third that measures test coverage. That approach allows designers unfamiliar with the original code to easily read it, understand how it functions and reuse portions within the same project or on future projects. It also allows the original code designers to more easily maintain and modify their code over time.

Need in-house standard
Good code hygiene also implies that developers follow a consistent coding style that adheres to some agreed-upon design standard. To enforce that methodology, project managers must identify and define an in-house standard that meets those goals. Just as critical are the implementation of regular design and code reviews to assure correctness, readability and maintainability. Those reviews can also serve as a vehicle to cross-train development team members so they are familiar with different elements of the development project.

Any functional-verification methodology designed to maximize the reuse of resources both within a project and from project to project must leverage existing resources as well. Designers should reuse existing components from other in-house developers, third parties and tool vendors to the greatest extent possible. Engineers at Mint Technology have developed a verification testbench for ARM-based systems based on thos e principles.

Called Braccio, this verification environment was designed to be a complete and portable verification environment for ARM9-based SoC designs. The Braccio testbench uses shared memory and multiple threads of execution to provide simultaneous stimulus to devices attached to the Amba High Performance (AHB) and Amba Peripheral Buses (APB) used on the ARM9 processor.

It features a stimulus generator for each of the devices in the system, a protocol checker for the AHB and APB and coverage checkers for each unique interface. Designers used the ARM Design Simulation Model from LSI Logic Corp. and ARM Ltd. to execute ARM core code, and a developer's kit with a compiler and debugger from LSI Logic to support code development.

Extensive reuse
In the Braccio project Mint designers made extensive reuse of existing module-level testbenches and tests written in VHSIC hardware description language with dedicated ARM core code for the USB, universal asynchronous receiver-tra nsmitter, interrupt control unit and general-purpose input/output blocks. While the testbenches and tests were reused to verify the blocks at the module level, new tests were created to support system-level testing with those devices.

Tool vendors are also a particularly valuable source of reusable components. For instance, Verisity Design Inc. offers as part of its e-verification component portfolio models of masters and slaves for the Amba bus used in the ARM9 processor. The tool kit for verifying Amba-based designs also includes stimulus generators and checkers. All of those were used in Mint's Braccio project.

As long as ASICs continue to grow in density and performance, the functional verification phase of the design cycle will continue to present major challenges for designers. By building a functional verification methodology predicated on a philosophy of software reuse designers can significantly reduce the time and resources required to verify their design while ensuring that their p roject meets aggressive time-to-market goals.