Minimal Effort Chip Design Using IP

By Aseem Gupta, Ph.D., Freescale Semiconductor

Abstract

In order to speed up design cycles and to reduce development costs, use of external IP is increasingly becoming more popular. However, this IP based design is not free of considerable effort and saves only about half of the effort required to develop the IP internally. The concept of Intelligent Design Automation (IDA) is presented here which uses intelligent algorithms such as matchmaking algorithm, rating systems, fuzzy logic, and multi-criteria optimization. This paper also presents the idea of IP Integration Automation,or I2A, tools. Much of the technology required for these concepts to become reality already exists in various forms and is in use for a different class of solutions.

I. INTRODUCTION

With the objective of accelerating the design cycle, companies are increasingly adopting IP (Intellectual Property) based design. IPbased design refers to the integration of complex components which are pre-designed and well tested. Using IP from an external vendor reduces the cost, effort, time, and risk of internal IP development and in some instances, the IP itself may be another company’s proprietary property. Today there are products in the market from major semiconductor companies in which more than 80% of the blocks are IP from external sources [1]. Silicon IP such as the IP which enables USB 3.0, HDMI, PCIe, SATA etc. is divided in to Soft-IP and Hard-IP. Soft-IP refers to the RTL code which can be synthesized in to respective USB 3.0 and HDMI controllers. These controllers are ASICs and have communication buses, internal memories etc. Hard-IP is the synthesized physical IP generally delivered as GDS-II files. A key thing to note is that Soft-IP is technology node independent and the same IP can be reused multiple times over many generations of technology nodes. Hard-IP on the other hand is technology dependent and can be reused within the same technology node. Hard-IP at TSMC40LP is specific to the process and cannot be used with any other foundry or at any other node. Most commonly industry trades the controllers in the form of Soft IP such as HDMI transmitter/receiver and USB host/device controllers and the most commonly traded hard-IP is PHY. PHY, short for ’Physical’, is the physical medium which connects the controllers inside the chip to the wires of the chip. PHY converts the data between analog and digital domains and also serializes/de-serializes it. HDMI PHY, USB PHY etc. are usually available in the market for popular technology nodes.

Unfortunately, IP based design is not as simple, firm, organized, and safe as it sounds. The process is fraught with risks and requires a lot of manual effort and careful planning. However, this process has a great scope for automation using intelligent algorithms. The purpose of this paper is to move a step closer to ’lights out’ approach towards design and manufacturing of computer chips. The ideas presented in this paper should be considered wild and crazy because of the assumption it makes regarding the adaptability of automation software and the level of trust placed in their outcomes. This paper suggests the radical approach of Intelligent Design Automation or IDA which uses intelligent algorithms such as matchmaking algorithm, rating systems, fuzzy logic, multi-criteria optimization, and self generating code.

Fig. 1. IP Based SoC Design Flow

II. INTELLIGENT DESIGN AUTOMATION

A part of the IP-design flow is shown in Figure 1. Our wild and crazy approach aims to navigate through this process in an automated manner or with the least amount of human intervention. The approach and the different steps of this flow can be explained using a simple example. Let this be a simple product specification:

Fig. 2. Chip Specification

An intelligent algorithm such as those used by popular job and dating sites can be used to scan this specification and identify keywords such as those underlined in the above specification [2]. These keywords are then mapped to a list of IP components for the proposed chip. Other components such as processor and communication architecture form the boiler plate for any system-on-chip (SoC). This list may look similar to this:

The next step is to perform architectural exploration at the system level. There are three main purposes of this step:

1. To determine if the IP list is complete and the different IPs are compatible with each other.
2. To determine the parameters for each of the IP components so that the resultant chip meets design constraints such as performance and power. For example, for the USB controllers, this step will determine the width of the datapath, operating frequency of circuits, and speed of the AMBA buses inside the controllers.

Fig. 3. Generated IP List

3. To use this model as part of the virtual platform which can be used to write operating system and other software for the chip [4]. The expectation from this step is to traverse the vast exploration space and find the right configuration for all the IP components. Our proposed idea is to use SystemC based platforms and a library of high level models for the IP to create this virtual model of the chip and then identify the parameters for the IP [5].

After the parametric requirements for the IP are determined, the task is to select a suitable IP vendor. If there are no IP vendors who provide the IP with the required parameters the step of architectural exploration must be repeated under new constraints. This situation arises more often than commonly imagined. For example, IP may use second generation AMBA AHB bus instead of the advanced AMBA AXI bus. If there are multiple vendors who can provide the IP, the selection of a vendor is not merely a matter of going with the cheapest option. The $ cost of the IP must be balanced with several other factors such as:

1. quality of the IP, often reported as number of bugs found in the IP on a weekly basis,
2. maturity status of the IP, reported as the number of successful chip tapeouts,
3. certification of the IP by respective organizations,
4. percentage of verification coverage of the IP,
5. built in self tests and waveform generation capabilities included in the IP, and
6. the time it will take to test the IP on the chip which is important given the high demand of tester time.

It is a very critical task to select the right IP ’partner’ to provide external IP and to manage the relationship on a continuing basis. We propose an intelligent selection algorithm which uses the above factors as metrics to rate the vendors and the IP based on a rating system similar to those used by popular internet auction sites [3]. Fuzzy logic algorithms can also assist with these decisions.

The IP delivered from different vendors must be integrated with each other and with IP developed in house in a company. Integration of IP is the major challenge today and much of the System on Chip (SoC) design today is about integration. The integration effort alone for an IP is about 40% of the effort to create the IP internally. It has been estimated that up to 65% of design time for an SoC is spent in integrating the IP [1]. Even when another SoC is designed which is a derivative of this SoC, the integration work must be repeated. There is a lack of integration tools in the market today. Just like the industry stepped up to create EDA (Electronic Design Automation) tools, there is a need for I2A (IP Integration Automation) tools. Some of the basic technology required for I2A tools exists today in the form of system level design tools. The task of I2A tools becomes much easier if standardized IP such as USB are on the chip. The assumption which our imagination makes here is that IP will be standardized to the extent of becoming a commodity. The I2A tools will be able to verify that different IP blocks connect to each other correctly. This will be made possible by standardizing interfaces. One small step in this direction is the development of PHY Interface for the PCI Express or PIPE Interface. The intelligence in these tools will be able to look at the IP’s parameters and generate an interface code. Connecting the pins, that too with the right polarity, on the IP will be automated using one of two approaches:

1. propagating a standard pin naming convention among IP providers, or
2. using the behavioral information about the IP to determine pin connectivity.

III. PREDICTED RESULTS

After following all the steps described in the last section, IDA methodology outputs an SoC design as shown in Fig. 4. This is then verified intensively using Verification IP (VIP) [6]. This is then followed by other physical design steps before tapeout.

Fig. 4. SoC Designed

IV. CONCLUSION

IP based design saves only about half of the effort required to develop the IP internally. There is need for Intelligent Design Automation (IDA) which will use intelligent algorithms to automate this process. Since most of the effort is spent in IP integration, a key component of IDA will be IP Integration Automation (I2A) tools. Hopefully, the future will bring such automation methods in to existence and increase designer productivity manifold.

REFERENCES

[1] R. Goering, “SoC Design Managers Cite IP Integration Challenges,” Cadence Inc. Blogs, June 24, 2010.

[2] S. Mohaghegh, “An Ontology Driven Matchmaking Process,” World Automation Congress, 2004.

[3] L. Kaiser, “The Official eBay Guide,” Simon Schuster, New York, 1999.

[4] Virtual Platforms, www.virtutech.com.

[5] S. Swan et. al, “System Design with SystemC,” Springer, 2002.

[6] D. Lin, “Verification IP for IP verification,” EETimes, July 2004.