Using verification coverage with formal analysis

Vinaya Singh, Joseph Hupcey III, Cadence Design Systems Inc.
EEtimes (4/13/2011 9:13 AM EDT)

Introduction

Verification engineers are increasingly using coverage metrics such as code coverage and functional coverage to guide the verification process to completion. These metrics, however, were developed specifically for simulation. Many contemporary verification flows also include formal analysis tools that provide exhaustive block-level proofs based on properties or assertions. The level of coverage provided by these tools needs to be evaluated, too – but it’s necessary to understand how formal “coverage” differs from simulation coverage, and how formal coverage results can reinforce, or in some cases even replace, coverage created by simulation engines.

In metric-driven verification flows, an executable verification plan tracks simulation coverage metrics on an ongoing basis, using the metrics to evaluate the completion of the verification process. As a result, engineers can quickly see whether a block is completely verified, or if further tests are needed. Steps of the process include developing the verification plan, constructing tests, executing tests, and measuring and analyzing coverage metrics.

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