English
Application Driven Network on Chip Architecture Exploration & Refinement for a Complex SoC
By Jean-Jacques Lecler and Gilles Baillieu, Arteris.
This peer-reviewed technical journal article is published in Springer Verlag's Design Automation for Embedded Systems Journal.
Abstract
This article presents an overview of the design process of an interconnection network, using the technology proposed by Arteris. Section 2 summarizes the various features a NoC is required to implement to be integrated in modern SoCs. Section 3 describes the proposed top-down approach, based on the progressive refinement of the NoC description, from its functional specification (Sect. 4) to its verification (Sect. 8). The approach is illustrated by a typical use-case of a NoC embedded in a hand-held gaming device. The methodology relies on the definition of the performance behavior and expectation (Sect. 5), which can be early and efficiently simulated against various NoC architectures. The system architect is then able to identify bottle-necks and converge towards the NoC implementation fulfilling the requirements of the target application (Sect. 6).
1- On chip interconnect fundamentals
On a SoC, intellectual property blocks (IPs) communicate over an interconnect system using transactions. A transaction is the operation of reading or writing some bytes of data at some addresses in a memory space. Transactions are composed of a request which goes from an initiator to a target and contains at least the address and data in the case of a write operation; and a response flowing back from the target to the initiator, with some status and data in case of read operation. The physical interface between IPs and the interconnect system are sockets, usually synchronous, with a master side and a slave side. A number of different socket protocols have been defined by the SoC industry (OCP, APB, AHB, AXI, STBus, DTL, etc.). Sometimes, transactions have to be converted between the initiator socket and the target socket of an interconnect, for instance if both socket protocols are not identical. Such conversions must preserve the byte transfer semantics, i.e. the functionality of the transaction.
|
E-mail This Article | 
|
|
Printer-Friendly Page |
|
||||||
Arteris Hot IP
Related Articles
- An HDTV SoC Based on a Mixed Circuit-Switched / NoC Interconnect Architecture (STBus/VSTNoC)
- SoC design: What's next for NoCs?
- Accelerating SoC Evolution With NoC Innovations Using NoC Tiling for AI and Machine Learning
- SoC NoCs: Homegrown or Commercial Off-the-Shelf?
- SoC design: When is a network-on-chip (NoC) not enough?
New Articles
- Nexus: A Lightweight and Scalable Multi-Agent Framework for Complex Tasks Automation
- How the Ability to Manage Register Specifications Helps You Create More Competitive Products
- EAVS - Electra IC Advanced Verification Suite for RISC-V Cores
- Why RISC-V is a viable option for safety-critical applications
- Dimensioning in 3D space: Object Volumetric Measurement by Leveraging Depth Camera-based Reconstruction on NVIDIA Edge devices
Most Popular
- System Verilog Assertions Simplified
- System Verilog Macro: A Powerful Feature for Design Verification Projects
- UPF Constraint coding for SoC - A Case Study
- Understanding Logic Equivalence Check (LEC) Flow and Its Challenges and Proposed Solution
- Enhancing VLSI Design Efficiency: Tackling Congestion and Shorts with Practical Approaches and PnR Tool (ICC2)