Down & dirty with HW/SW co-design: Part 3 - Cosynthesis of multiprocessors
Wayne Wolf
EETimes (6/21/2011 12:08 AM EDT)
Following on Part 1 and Part 2 in this series, we now will reconsider hardware/software co-design for more general multiprocessor architectures.
Many useful systems can be designed by hardware/software partitioning algorithms based on the CPU+ accelerator template. Hardware/software partitioning can also be used to design PEs that are part of larger multiprocessors.
But if we want to design a complete application-specific multiprocessor system, we need to use more general co-synthesis algorithms that do not rely on the CPU+ accelerator template.
In the most general case, all these tasks are related. Different partitions of functionality into processes clearly changes scheduling and allocation. Even if we chose a partitioning of functions, scheduling, allocating, and binding are closely related.
We want to choose the processing element for a process - both the general allocation and the binding to a specific type - based on the overall system schedule and when that process has to finish.
But we can't determine the schedule and the completion time of a process until we at least choose an allocation and most likely a binding. This is the Gordian knot that co-synthesis designers must face-the set of intertwined problems that must somehow be unraveled.
E-mail This Article | Printer-Friendly Page |
Related Articles
- Down & dirty with HW/SW co-design: Part 4 – Multi-objective optimization
- HW/SW co-verification basics: Part 3 - Hardware-centric methods
- HW/SW co-verification basics: Part 2 - Software-centric methods
- HW/SW co-verification basics: Part 1 - Determining what & how to verify
- Specifying a PLL Part 3: Jitter Budgeting for Synthesis
New Articles
Most Popular
- System Verilog Assertions Simplified
- System Verilog Macro: A Powerful Feature for Design Verification Projects
- Enhancing VLSI Design Efficiency: Tackling Congestion and Shorts with Practical Approaches and PnR Tool (ICC2)
- Synthesis Methodology & Netlist Qualification
- Streamlining SoC Design with IDS-Integrate™