English
Reducing Turnaround Time with Hierarchical Timing Analysis
Sunil Walia, Synopsys
EETimes (10/3/2011 10:32 AM EDT)
The semiconductor industry accepts two facts: designs continue to grow in size and complexity, and time-to-market pressure is higher than ever. I’ll use the ‘smart phone’ as an example to make my point. On a smart phone you can now talk, text, IM, take pictures and videos, play games and perform a host of other tasks. Question: How is this possible? Answer: By integrating multiple functionalities capable of simultaneous interaction onto a single chip. Question: How do you make this happen within the same amount of time you are given as the last chip? Answer: Design reuse.
As design evolution continues, packing lots more on a single die, ‘design reuse’ has become a common technique. There is reuse of IPs, flows, and methodologies – all causing the design size growth to sometimes surpass Moore’s Law. However, designers are feeling the squeeze between packing tons of functionality on one end and experiencing no relaxation in time-to-market requirements at the other. Market dynamics dictate that if you snooze, you lose.
|
E-mail This Article | 
|
|
Printer-Friendly Page |
|
||||||
Synopsys, Inc. Hot IP
Related Articles
- Reducing Debug time for Scan pattern using Parallel Strobe Data (PSD) Flow
- Methodology to reduce Run Time of Timing/Functional Eco
- Distorted Waveform Phenomena in 7nm Technology Node and its Impact on Signoff Timing Analysis
- Static timing analysis: bridging the gap between simulation and silicon
- Reducing power in AMD processor core with RTL clock gating analysis
New Articles
- Accelerating RISC-V development with Tessent UltraSight-V
- Automotive Ethernet Security Using MACsec
- What is JESD204C? A quick glance at the standard
- Optimizing Power Efficiency in SOC with PVT Sensor-Assisted DVFS Technology
- Bandgap Reference (BGR) Circuit Design and Transient Analysis in 90nm VLSI Technology
Most Popular
- System Verilog Assertions Simplified
- Accelerating RISC-V development with Tessent UltraSight-V
- System Verilog Macro: A Powerful Feature for Design Verification Projects
- Understanding Logic Equivalence Check (LEC) Flow and Its Challenges and Proposed Solution
- Design Rule Checks (DRC) - A Practical View for 28nm Technology