English
Assertion-based verification in mixed-signal design
Prabal Bhattacharya and Don O'Riordan
10/17/2011 12:01 PM EDT
Introduction
Assertion-based verification (ABV) is a powerful verification approach that has been proven to help digital IC architects, designers, and verification engineers improve design quality and reduce time to market. But ABV has rarely been applied to analog/mixed-signal verification. This article looks at challenges in analog/mixed-signal verification, evaluates how the ABV concept can address some of those challenges, and shows how languages such as Property Specification Language (PSL) and SystemVerilog Assertions (SVA) can be used to write complex analog/mixed-signal assertions.
Assertions, by definition, capture the intended behavior of a design. In verification terminology, ABV can be positioned both as a white-box and a black-box approach in that the user can create properties (or asserted behaviors) that can monitor the design deep within the hierarchy, reaching the internals of the design blocks as well as the interfaces of the design blocks.
Assertions are written both during development of the design and the verification environment. Both designers and verification engineers can consequently be involved in identifying requirements and capturing them as assertions.
So where do mixed-signal assertions fit in?
|
E-mail This Article | 
|
|
Printer-Friendly Page |
|
||||||
Cadence Design Systems, Inc. Hot IP
Related Articles
- Mixed-signal SOC verification using analog behavioral models
- The Challenges and Benefits of Analog/Mixed-Signal and RF System Verification above the Transistor Level
- Efficient Verification and Virtual Prototyping of Analog and Mixed-Signal IP and SOCs Using Behavioral Models
- Mixed-Signal Verification for USB 2.0 Physical Layer IP
- Analog behavioral models reduce mixed-signal LSI verification time
New Articles
- Quantum Readiness Considerations for Suppliers and Manufacturers
- A Rad Hard ASIC Design Approach: Triple Modular Redundancy (TMR)
- Early Interactive Short Isolation for Faster SoC Verification
- The Ideal Crypto Coprocessor with Root of Trust to Support Customer Complete Full Chip Evaluation: PUFcc gained SESIP and PSA Certified™ Level 3 RoT Component Certification
- Advanced Packaging and Chiplets Can Be for Everyone
Most Popular
- System Verilog Assertions Simplified
- System Verilog Macro: A Powerful Feature for Design Verification Projects
- UPF Constraint coding for SoC - A Case Study
- Dynamic Memory Allocation and Fragmentation in C and C++
- Enhancing VLSI Design Efficiency: Tackling Congestion and Shorts with Practical Approaches and PnR Tool (ICC2)