Single event effects (SEEs) in FPGAs, ASICs, and processors, part I: impact and analysis

Dagan White, Xilinx
EETimes (12/14/2011 1:47 PM EST)

Single-event effects (SEEs) are of a growing concern in high-reliability system development, yet there is much disparity among users of application-specific integrated circuits (ASICs) and field-programmable gate arrays (FPGAs) with regard to understanding how susceptible their designs might be. The avionics and industrial system development guidance that currently exists is only broadly beginning to consider SEEs and their impact on system reliability. Unfortunately, standards such as DO-254, DO-178, ARP 4754, ARP 4761, and IEC 61508 provide little or no direction on how to handle SEEs. This white paper highlights concerns regarding effects of SEEs on ASICs and FPGAs and points to analysis and mitigation techniques for handling SEEs.

All sub-micron integrated electronics devices are susceptible to SEEs to some degree. The effects can range from transients causing logical errors, to upsets changing data, to destructive single-event latch-up (SEL). Traditionally, FPGAs were targeted as being more sensitive due to their use of SRAM for the configuration storage. As dimensions shrink to below 90 nm, SEEs in all devices, including ASICs, FPGAs, and application-specific standard products (ASSPs) must be considered.

Although targeted to an avionics audience, this article has broad applicability to any industry in which safety and reliability are of critical importance. It should be useful to a wide audience comprised of system architects, engineering and program managers, and certification authorities.

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