English
Understanding Skew in 100GBASE-R4 applications
Tim Warland, AppliedMicro
EETimes (12/14/2011 3:35 PM EST)
The 100GBASE-R4 physical layer device converts 10-lanes running 10Gbps (CAUI) to 4-lanes running 25Gbps. The conversion process is data agnostic with no provision for rate adaptation, consequently skew management is an integral part of end-to-end system performance.
Recently ratified, the 100Gigabit Ethernet Standard, (IEEE802.3ba) defines a 100GBASE-LR4 and 100GBASE-ER4 interface for optical interfaces on single-mode fiber. The architecture includes the Physical Coding sub layer (PCS), connected on one side to the reconciliation sub-layer (RS) and MAC and to the PMA/PMD on the other side. Actually implementations are more likely to combine the PCS and PMA with the RS and MAC and interface to a second PMA and PMD (referred to as the PHY)
|
E-mail This Article | 
|
|
Printer-Friendly Page |
|
||||||
Related Articles
- Timing Optimization Technique Using Useful Skew in 5nm Technology Node
- Understanding the contenders for the Flash memory crown
- Understanding mmWave RADAR, its Principle & Applications
- Understanding Timing Correlation Between Sign-off Tool and Circuit Simulation
- Understanding the Importance of Prerequisites in the VLSI Physical Design Stage
New Articles
- Accelerating RISC-V development with Tessent UltraSight-V
- Automotive Ethernet Security Using MACsec
- What is JESD204C? A quick glance at the standard
- Optimizing Power Efficiency in SOC with PVT Sensor-Assisted DVFS Technology
- Bandgap Reference (BGR) Circuit Design and Transient Analysis in 90nm VLSI Technology
Most Popular
- Accelerating RISC-V development with Tessent UltraSight-V
- System Verilog Assertions Simplified
- Synthesis Methodology & Netlist Qualification
- System Verilog Macro: A Powerful Feature for Design Verification Projects
- Enhancing VLSI Design Efficiency: Tackling Congestion and Shorts with Practical Approaches and PnR Tool (ICC2)