How formal MDV can eliminate IP integration uncertainty
The increased deployment of silicon intellectual property (IP) blocks is vital to boosting productivity in the development of large, complex system-on-chip (SoC) designs. But the increase in SoC design productivity is not matched by as great an increase in SoC verification productivity. Managers and engineers still struggle with a persistent “verification productivity gap.” Why? Because there is a persistent IP verification quality gap, too. The resulting uncertainty about the original verification quality of individual IP blocks often requires time-consuming remedial verification by the SoC design team. The alternative is to risk SoC design failure because of inadequate IP verification, which ultimately delays the project even more.
This article outlines how the latest formal metric-driven verification (MDV) methodology and technologies can eliminate integration uncertainty through the automatic generation of Accellera-defined coverage metrics, without the assistance of simulation. This formal MDV methodology measures not only the usual control coverage, but also observation coverage — a serious missing link in many other MDV approaches. The methodology is easily integrated into existing MDV flows or can be used stand-alone.
![]() |
E-mail This Article | ![]() |
![]() |
Printer-Friendly Page |
|
Related Articles
- It's Not My Fault! How to Run a Better Fault Campaign Using Formal
- How formal verification saves time in digital IP design
- How to Save Time and Improve Communication Between Semiconductor Design and Verification Engineers
- How control electronics can help scale quantum computers
- How Low Can You Go? Pushing the Limits of Transistors - Deep Low Voltage Enablement of Embedded Memories and Logic Libraries to Achieve Extreme Low Power
New Articles
- Nexus: A Lightweight and Scalable Multi-Agent Framework for Complex Tasks Automation
- How the Ability to Manage Register Specifications Helps You Create More Competitive Products
- EAVS - Electra IC Advanced Verification Suite for RISC-V Cores
- Why RISC-V is a viable option for safety-critical applications
- Dimensioning in 3D space: Object Volumetric Measurement by Leveraging Depth Camera-based Reconstruction on NVIDIA Edge devices
Most Popular
- Nexus: A Lightweight and Scalable Multi-Agent Framework for Complex Tasks Automation
- System Verilog Assertions Simplified
- Synthesis Methodology & Netlist Qualification
- How the Ability to Manage Register Specifications Helps You Create More Competitive Products
- System Verilog Macro: A Powerful Feature for Design Verification Projects