Resistive RAM for next-generation nonvolatile memory

Bogdan Govoreanu, imec Leuven
EETimes (3/12/2012 1:25 PM EDT)

Since its introduction in 1988 by Toshiba1, NAND flash nonvolatile memory has undergone an unprecedented growth, becoming one of today’s technology drivers. Although NAND flash memory has scaled to 1x-nm feature sizes, shrinking cell sizes reduce the number of electrons stored on the floating gate. Resistive RAM (RRAM) provides an alternative. In this article, we review the main performance figures of hafnium-oxide (HfO2)-based RRAM cells4 from a scalability perspective, outlining their strengths as well as the main challenges ahead.

A NAND flash nonvolatile memory cell, usually a floating gate transistor, implements the memory function by charge stored on the floating gate. With a charge transfer mechanism onto/from the storage medium that relies on tunneling and a serial (string) architecture, NAND memory features high operating voltages (with associated chip area consumption for the on-chip voltage generation), rather long cell program/erase (P/E) times, and slow read-access times. These drawbacks are, however, compensated for by the very compact array architecture and extremely low energy-consumption-per-bit operation, which eventually enabled fabrication of high-density memory arrays, at low cost and with a chip storage capacity increasing impressively.

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