Ensuring Successful Third Party Intellectual Property (IP) Integration
Mohit Gupta (Open-Silicon) and Bernd Stamme (Kilopass)
3/26/2012 10:42 AM EDT
Today’s complex ASICs often leverage open-market IP to take advantage of reuse of standard functional blocks, and thereby improve time to market and development efficiency. However, the integration of that third-party IP, if done poorly, can lead to painful cost overruns and schedule delays. To ensure proper IP core integration, Open-Silicon has developed a detailed and comprehensive process involving close collaboration with IP partners and the SoC design team. This article will illustrate this process by showing how Open-Silicon and Kilopass worked together on a recent project to ensure success.
At the highest level, Open-Silicon employs a four-step process to ensure that the IP included in its design will achieve first-time silicon success. These steps include IP selection, IP procurement, IP qualification and IP integration. Each of these steps is detailed below.
![]() |
E-mail This Article | ![]() |
![]() |
Printer-Friendly Page |
|
Related Articles
- Verification of Third-Party CPU Intellectual Property
- Three Major Inflection Points for Sourcing Bluetooth Intellectual Property
- Design Rights Management of Intellectual Property (IP) Cores in SoPC designs
- Silicon Intellectual Property - Delivering value to customers
- Intellectual property security: A challenge for embedded systems developers
New Articles
- Density Management in Analog Layout Design: Addressing Issues and Ensuring Consistency
- Nexus: A Lightweight and Scalable Multi-Agent Framework for Complex Tasks Automation
- How the Ability to Manage Register Specifications Helps You Create More Competitive Products
- EAVS - Electra IC Advanced Verification Suite for RISC-V Cores
- Why RISC-V is a viable option for safety-critical applications
Most Popular
- System Verilog Assertions Simplified
- Enhancing VLSI Design Efficiency: Tackling Congestion and Shorts with Practical Approaches and PnR Tool (ICC2)
- System Verilog Macro: A Powerful Feature for Design Verification Projects
- An Outline of the Semiconductor Chip Design Flow
- Synthesis Methodology & Netlist Qualification