MIPI C-PHY v1.2 D-PHY v2.1 TX 3 trios/4 Lanes in TSMC (16nm, 12nm, N7, N6, N5, N3E)
2.5D ICs are more than a stepping stone to 3D ICs
Mike Santarini, Xilinx
EETimes (3/27/2012 2:04 PM EDT)
With Xilinx releasing last year the first commercially available 28nm, 2.5D Stacked Silicon Interconnect (SSI) device (the Virtex-7 2000T FPGA) followed by TSMC announcing full manufacturing and assembly support for 2.5D and 3D IC designs, the rest of the IC industry is starting to rev up efforts to make 2.5D and eventually 3D IC technology a mainstream reality.
2.5D has marked advantages of capacity, performance, system space and overall system power consumption over traditional single die implementations—3D promises to have even more. As a refresher, 2.5D, as implemented by Xilinx in the Virtex-7 2000T device, places several die (what Xilinx calls “slices”) side-by-side on a passive silicon interposer. Meanwhile, the industry envisions 3D ICs will stack two or more die (active-on-active) on top of each other and allow companies to achieve new levels of system integration by stacking the chips normally in a PCB in one or just a few devices (Figure 1).
The vision of a 3D IC is truly promising, but some industry watchers believe the 2.5D market is perhaps being too easily dismissed as a stepping stone to true 3D design. 2.5D has the distinct advantage of being already here today for some companies--and leveraging it takes only minor adjustments to current design flows and seemingly the manufacturing chain.
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