English
Automatic C-to-VHDL testbench generation shortens FPGA development time
Sunil Sahoo (Aldec) and Brian Durwood (Impulse)
EETimes (4/11/2012 12:05 PM EDT)
Verifying behavior early and often has become critical with FPGAs. Newer generations of FPGAs have gate counts that rival the largest custom ASICs of five years ago. This fact, coupled with the broad use of FPGA-embedded processor cores, has resulted in the increased use of FPGAs for complex, algorithmic processing logic as well as the traditional uses of glue and control logic. The use of FPGAs for complex processing can create an overall design that may combine C, VHDL and Verilog. This creates a challenge when it comes to verification, and a particular challenge to the new generation of FPGA users who are migrating over from software development to hardware acceleration.
New design C-based methods and new testbench generators enable developers to mix C and HDL. In this extended tool flow, the core application is developed in C. First level verification is performed in software simulation using Visual Studio or a comparable tool. After this functionality-only test, the developer selects a target FPGA or a target FPGA-enabled board and then verifies functionality at that level, either in-system or using a hardware simulator. The latter method saves time by reducing the iterations through FPGA place-and-route. A key productivity boost in this case is that the test files for the VHDL simulator are generated from the original C design files. There is no disconnect from design engineering to design for test.
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