English
Accelerate partial reconfiguration with a 100% hardware solution
S. Lamonnier, M. Thoris, M. Ambielle, Sagem DS (Safran Group)
EETimes (5/26/2012 12:39 PM EDT)
In many modern applications such as video processing, minimizing FPGA reconfiguration time is critical in order to avoid losing too many images. Partial reconfiguration is a technique that allows users to reconfigure a small part of the FPGA without impacting logical elements around it. For the human eye to see an image without flicker, the reconfiguration time must be less than 40 milliseconds. That’s very little time to reconfigure an entire device, save for the smallest FPGAs; and in certain specific applications, this reconfiguration time must be even less. Hence the appeal of partial reconfiguration: Because a partial bitstream is smaller than a full one, it takes less time to reconfigure.
At Sagem DS, we have devised a technique that allows FPGA designers to accomplish partial reconfiguration very fast. The ML507 [1] was the Xilinx reference board we used for testing and validating the solution and to measure timing. Typically, the components on this board are a Virtex-5 FPGA (XC5VFX70T-FFG1136), a CPLD (used as a routing component) and two XCF32P memories (Xilinx Platform Flash).
|
E-mail This Article | 
|
|
Printer-Friendly Page |
Related Articles
- How partial dynamic reconfiguration helped make an FSK demodulator
- Bridging software and hardware to accelerate SoC validation
- Partial reconfiguration in FPGA rapid prototyping tools
- An MDE Approach For Implementing Partial Dynamic Reconfiguration In FPGAs
- 20th Anniversary article: Full simulations with partial hardware
New Articles
- Quantum Readiness Considerations for Suppliers and Manufacturers
- A Rad Hard ASIC Design Approach: Triple Modular Redundancy (TMR)
- Early Interactive Short Isolation for Faster SoC Verification
- The Ideal Crypto Coprocessor with Root of Trust to Support Customer Complete Full Chip Evaluation: PUFcc gained SESIP and PSA Certified™ Level 3 RoT Component Certification
- Advanced Packaging and Chiplets Can Be for Everyone
Most Popular
- System Verilog Assertions Simplified
- System Verilog Macro: A Powerful Feature for Design Verification Projects
- UPF Constraint coding for SoC - A Case Study
- Dynamic Memory Allocation and Fragmentation in C and C++
- Enhancing VLSI Design Efficiency: Tackling Congestion and Shorts with Practical Approaches and PnR Tool (ICC2)