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NoC Silicon IP for RISC-V based chips supporting the TileLink protocol
Is the cost reduction associated with IC scaling over?
Zvi Or-Bach, MonolithIC 3D Inc.
EETimes (7/16/2012 12:20 PM EDT)
The last 50 years of the semiconductor industry have been all about the manifestation of Moore's Law with regard to the dimensional scaling of Integrated Circuits (ICs). As consumers of electronic devices, we all love to see better products at a lower cost with each and every new product cycle. But now storm clouds are forming, as was recently publicly expressed in the article Nvidia deeply unhappy with TSMC, claims 20nm essentially worthless.
Clearly, dimensional scaling is no longer associated with lower average cost per transistor. The chart below, published by IBS about a year ago, shows the diminishing benefit of cost reduction from dimensional scaling. In fact, the chart indicates that the 20nm node might be associated with higher cost than the previous node.
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