English
Mixed-signal SOC verification using analog behavioral models
The era of “Internet everywhere” is creating a spectrum of applications targeted toward low-power and mixed-signal design, in segments ranging from health care to automotive to communications. Meanwhile, design challenges such as intellectual-property selection and integration as well as SOC- and system-level verification are spawning a whole new class of problems for EDA tools.
Mixed-signal design engineers face increasing difficulties in design and verification of complex mixed-signal SOCs. In a survey of mixed-signal design engineers during the 2011 Mixed-Signal Tech on Tour, a worldwide series presented by Cadence Design Systems Inc, the 561 respondents identified mixed-signal verification as a top customer challenge.
The performance of Spice simulation is prominent in the difficulties being reported. Analog Spice and Fast-Spice simulators are orders of magnitude slower than digital simulators and are slower still when compared with emulators and hardware accelerators. A June 2011 Design Automation Conference panel discussed the need for analog design and verification to become more like digital—that is, to become more structured and more top-down. Verification planning tools are required, and debug methodologies such as ABV (assertion-based verification), MDV (metric-driven verification), and UVM (universal verification methodology)-like self-checking test benches must be created for analog/mixed-signal.
|
E-mail This Article | 
|
|
Printer-Friendly Page |
|
||||||
Cadence Hot IP
Related Articles
- Efficient Verification and Virtual Prototyping of Analog and Mixed-Signal IP and SOCs Using Behavioral Models
- Analog behavioral models reduce mixed-signal LSI verification time
- The Challenges and Benefits of Analog/Mixed-Signal and RF System Verification above the Transistor Level
- SoC Test and Verification -> Testing mixed-signal Bluetooth designs
- Simplifying analog and mixed-signal design integration
New Articles
- Accelerating RISC-V development with Tessent UltraSight-V
- Automotive Ethernet Security Using MACsec
- What is JESD204C? A quick glance at the standard
- Optimizing Power Efficiency in SOC with PVT Sensor-Assisted DVFS Technology
- Bandgap Reference (BGR) Circuit Design and Transient Analysis in 90nm VLSI Technology
Most Popular
- Accelerating RISC-V development with Tessent UltraSight-V
- System Verilog Assertions Simplified
- Synthesis Methodology & Netlist Qualification
- System Verilog Macro: A Powerful Feature for Design Verification Projects
- Enhancing VLSI Design Efficiency: Tackling Congestion and Shorts with Practical Approaches and PnR Tool (ICC2)