Stretching the Dynamic Range of ADCs - A case study
Robert Fifield, RFEL
EETimes (10/9/2012 10:26 AM EDT)
Whether your application is focused on wireless communications or instrumentation, the performance bottleneck is often the dynamic range of the analog-to-digital converter (ADC). Dynamic range is often a key parameter within signal processing systems and a shortfall can limit the quality and range of signals that can be received. The technical progress made on improving this gateway between the analog and digital world has not kept pace with Moore’s law[1] because the challenges are more fundamental than simply reducing transistor sizes. Methods to increase ADC dynamic range are always of interest although each solution often suits particular applications.
As an example of pushing ADC dynamic range beyond what is currently available, the engineers at RFEL were confronted with an application where a customer required an analog-to-digital conversion with a 74dB dynamic range at 800MSPS. Most available ADCs at this rate were typically 52dB, i.e. 8.3 effective number of bits[2] (ENOB). This represented a significant 22dB shortfall, which had to be resolved for the project to be feasible.
Various techniques for extending dynamic range were considered taking into account their advantages and disadvantages:
E-mail This Article | Printer-Friendly Page |
|
Related Articles
New Articles
- Quantum Readiness Considerations for Suppliers and Manufacturers
- A Rad Hard ASIC Design Approach: Triple Modular Redundancy (TMR)
- Early Interactive Short Isolation for Faster SoC Verification
- The Ideal Crypto Coprocessor with Root of Trust to Support Customer Complete Full Chip Evaluation: PUFcc gained SESIP and PSA Certified™ Level 3 RoT Component Certification
- Advanced Packaging and Chiplets Can Be for Everyone
Most Popular
- System Verilog Assertions Simplified
- System Verilog Macro: A Powerful Feature for Design Verification Projects
- UPF Constraint coding for SoC - A Case Study
- Dynamic Memory Allocation and Fragmentation in C and C++
- Enhancing VLSI Design Efficiency: Tackling Congestion and Shorts with Practical Approaches and PnR Tool (ICC2)