English
Wi-Fi 6 (ax)+BLEv5.4+15.4 Dual Band RF IP for High-End Applications.
High-yield, high-performance memory design
Trent McConaghy - Solido Design Automation
EETimes (11/5/2012 10:33 AM EST)
In TSMC 28nm process and as process nodes scale, achieving target yields can be extremely challenging. Nowhere is this truer than for memory circuits, which aggressively adopt next bleeding-edge process nodes to help meet increasingly tighter performance specifications and higher levels of integration.
This article reviews the challenges raised by process variation, and in particular for memory with its high-sigma components. It then discusses an approach to address variation with accurate statistical MOS modeling, plus the ability to analyze billions of Monte Carlo samples in minutes. This solution is now in place and rapidly gaining adoption.
|
E-mail This Article | 
|
|
Printer-Friendly Page |
Related Articles
- Optimizing high-performance CPUs, GPUs and DSPs? Use logic and memory IP - Part I
- Attofarad accuracy for high-performance memory design
- High-Performance, High-Precision Memory Characterization
- Transactional Level Modeling (TLM) of a High-performance OCP Multi-channel SDRAM Memory Controller
- Infrastructure ASICs drive high-performance memory decisions
New Articles
- Understanding MACsec and Its Integration
- Discover new Tessent UltraSight-V from Siemens EDA, and accelerate your RISC-V development.
- The Critical Factors of a High-performance Audio Codec - What Chip Designers Need to Know
- Density Management in Analog Layout Design: Addressing Issues and Ensuring Consistency
- Nexus: A Lightweight and Scalable Multi-Agent Framework for Complex Tasks Automation
Most Popular
- System Verilog Assertions Simplified
- Synthesis Methodology & Netlist Qualification
- System Verilog Macro: A Powerful Feature for Design Verification Projects
- Enhancing VLSI Design Efficiency: Tackling Congestion and Shorts with Practical Approaches and PnR Tool (ICC2)
- UPF Constraint coding for SoC - A Case Study