English
32G Multi Rate Very Short Reach SerDes PHY - GlobalFoundries 12LP and 12LPP
Predicting PLL reference spur levels due to leakage current
Michel Azarian, Sr. Applications Engineer, and Will Ezell, Mixed Signal Products, Linear Technology
EETimes (11/9/2012 12:22 PM EST)
A simple model can be used to accurately predict the level of reference spurs due to charge pump and/or op-amp leakage current in a phased-locked loop system. Knowing how to predict these levels helps pick loop parameters wisely during the early stages of a PLL system design.
Quick review of PLLs
The phase-locked loop (PLL) is a negative feedback system that locks the phase and frequency of a higher frequency device (usually a voltage controlled oscillator (VCO) whose phase and frequency are not very stable over temperature and time to a more stable and lower frequency device (usually a temperature compensated or oven-controlled crystal oscillator, (TCXO or OCXO). As a black box, the PLL can be viewed as a frequency multiplier.
|
E-mail This Article | 
|
|
Printer-Friendly Page |
Related Articles
- Specifying a PLL Part 1: Calculating PLL Clock Spur Requirements from ADC or DAC SFDR
- Keeping leakage current under control
- Analysis and Summary on Clock Generator Circuits and PLL Design
- Bandgap Reference (BGR) Circuit Design and Transient Analysis in 90nm VLSI Technology
- Achieving Your Low Power Goals with Synopsys Ultra Low Leakage IO
New Articles
- RISC-V in 2025: Progress, Challenges,and What's Next for Automotive & OpenHardware
- Understanding MACsec and Its Integration
- Discover new Tessent UltraSight-V from Siemens EDA, and accelerate your RISC-V development.
- The Critical Factors of a High-performance Audio Codec - What Chip Designers Need to Know
- Density Management in Analog Layout Design: Addressing Issues and Ensuring Consistency
Most Popular
- RISC-V in 2025: Progress, Challenges,and What's Next for Automotive & OpenHardware
- System Verilog Assertions Simplified
- System Verilog Macro: A Powerful Feature for Design Verification Projects
- UPF Constraint coding for SoC - A Case Study
- A Heuristic Approach to Fix Design Rule Check (DRC) Violations in ASIC Designs @7nm FinFET Technology