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TSMC GF Intel Samsung Fractional-N Frequency Synthesizer PLL
Predicting PLL reference spur levels due to leakage current
Michel Azarian, Sr. Applications Engineer, and Will Ezell, Mixed Signal Products, Linear Technology
EETimes (11/9/2012 12:22 PM EST)
A simple model can be used to accurately predict the level of reference spurs due to charge pump and/or op-amp leakage current in a phased-locked loop system. Knowing how to predict these levels helps pick loop parameters wisely during the early stages of a PLL system design.
Quick review of PLLs
The phase-locked loop (PLL) is a negative feedback system that locks the phase and frequency of a higher frequency device (usually a voltage controlled oscillator (VCO) whose phase and frequency are not very stable over temperature and time to a more stable and lower frequency device (usually a temperature compensated or oven-controlled crystal oscillator, (TCXO or OCXO). As a black box, the PLL can be viewed as a frequency multiplier.
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