Four soft-core processors for embedded systems
Sven-Ake Andersson, Realtime Embedded
EETimes (1/8/2013 3:23 PM EST)
Many of you may have already read my blog called How to design an FPGA from scratch, which I started to write 2006 and which Max Maxfield wrote about in EE Times for the first time in 2007.
My latest blog describes the work I have performed at Realtime Embedded over the course of the past year. In this blog, I investigate four soft-core processors and use the same setup as in my first blog called “learning by doing.” This means that each soft processor will be implemented in an FPGA and the whole design process will be documented.
E-mail This Article | Printer-Friendly Page |
Related Articles
New Articles
- Quantum Readiness Considerations for Suppliers and Manufacturers
- A Rad Hard ASIC Design Approach: Triple Modular Redundancy (TMR)
- Early Interactive Short Isolation for Faster SoC Verification
- The Ideal Crypto Coprocessor with Root of Trust to Support Customer Complete Full Chip Evaluation: PUFcc gained SESIP and PSA Certified™ Level 3 RoT Component Certification
- Advanced Packaging and Chiplets Can Be for Everyone
Most Popular
- System Verilog Assertions Simplified
- System Verilog Macro: A Powerful Feature for Design Verification Projects
- UPF Constraint coding for SoC - A Case Study
- Dynamic Memory Allocation and Fragmentation in C and C++
- Enhancing VLSI Design Efficiency: Tackling Congestion and Shorts with Practical Approaches and PnR Tool (ICC2)