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Tackling large-scale SoC and FPGA prototyping debug challenges
Brad Quinton, Tektronix
EETimes (1/21/2013 11:06 AM EST)
When designing complex ASICs, such as a highly-integrated system-on-chip (SoC), engineers are highly motivated to perform comprehensive verification under as real-world operating conditions as possible to ensure that bugs can be identified and corrected before final tapeout. The source of the motivation, of course, is the high-cost and time required to re-spin an ASIC.
While discovering and tracking down the root cause of bugs can be challenging in the best of circumstances, inherent limitations in the various technologies available to ASIC designers for verification testing make the job much harder as each involves a variety of tradeoffs. Now, however, new technologies are emerging that offer the promise of much more efficient and less time intensive debug processes using FPGA prototypes.
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