Verification methodology serves memory subsystem

Verification methodology serves memory subsystem
By Jeremy Yiu, EEdesign
May 16, 2002 (5:25 p.m. EST)
URL: http://www.eetimes.com/story/OEG20020516S0066

AcceLight Networks recently developed a verification environment and methodology for a complex datapath controller (DPC). To accomplish this task, AcceLight used Denali Software's MMAV and Synopsys' Vera products. The DPC is used in high-speed line cards to provide temporary storage for data packets arriving at one or more of the input ports or destined for one or more of the output ports. As shown in Figure 1, the DPC typically communicates with a traffic management engine (TME) that directs the DPC as to where and when to de-queue a packet to the downstream device.

Figure 1 - System block diagram

Denali's MMAV product, along with Synopsys' Vera, was instrumental in providing a sophisticated and flexible verification testbench. To verify the DPC device under test (DUT), Vera was used to create a behavioral model of the DUT, a bus-functional model of the related devices, a traffic generator, data monitors, and data checkers. The Verilog RTL DPC was used along with Denali memory models to complete the memory subsystem.

Vera provides a shell to link Vera and Verilog together. In addition, it provides mechanisms to call Vera tasks directly from Verilog. Denali's memory models provide a C interface to allow direct communication between the Vera testbench and the memory devices, while maintaining coherency within the Verilog simulation. The following conceptual diagram illustrates how Vera, Denali, and Verilog co-exist in a typical verification environment.

Figure 2 - Denali/Vera logical flow diagram

Memory selection, configuration and integration
Fast Cycle RAM (FCRAM) is a revolutionary DRAM core architecture that achieves SRAM-like performance with DRAM technology by using a proprietary pipeline operation and hidden pre-charge to reduce the random access cycle time. It was chosen for the memory subsystem due to these desired characteristics.

In this design, the DPC required a number of 64-bit memory interfaces for temporary storage of packet information. The memory was implemented using 256Mbit (4M x 4 banks x 16 bit) FCRAM devices. These 16-bit wide devices were combined in groups of four to comprise each separate 64-bit wide memory interface.

Ensuring correct memory behavior while interacting with many separate FCRAM memory devices was a key challenge in developing a robust memory subsystem verification environment. Verifying that the DPC correctly accessed these memory devices, by following the proper protocol and timing requirements, was a necessity. Denali's MMAV provided accurate and robust FCRAM models to ensure the DPC's correctness. Together with accurate protocol and timing checks, Denali's MMAV models also integrate directly into Synopsys' Vera environment.

Testbench design
Synopsys' Vera testbench automation tool was used to accelerate module and s ystem level verification. With Vera, it is easy to quickly model the target environment at a high-level of abstraction, essentially creating a virtual prototype. This target environment included complex data monitors and checkers, traffic generators, and bus functional models of upstream and downstream devices.

Vera includes rich object-oriented constructs and key hardware-oriented concepts like clock timing, asynchronous timing, and signals (including unknown values.) This made it possible to create a Vera behavioral model in less time than a Verilog behavioral model, and with fewer lines of code. This behavioral model allowed us to develop and debug the traffic generators and checkers before the Verilog RTL was completed. By allowing for the concurrent creation of the testbench and Verilog RTL design, the testbench was ready before the RTL description, saving significant time in the schedule.

This combination of Vera behavioral models and RTL descriptions was especially useful for multi-chip sim ulations, where the configuration and connections between various blocks was controlled by Vera scripts. The Vera dynamic signal binding capability allows Vera inputs or outputs to be connected to different RTL signals or nodes at run time, enabling dynamic configuration control.

For stimulus generation, we relied on the native randomization and data packing capabilities in Vera, as well as the Vera class structures that make packet definition straightforward. The data monitors implement a self-checking capability that relies on the Vera mailbox construct to synchronize separate threads of activity and to queue complex data objects.

Another key decision in using Vera was its direct integration with Denali's MMAV. Because of the ability to directly interact with Denali's C-based memory devices from Vera, simulation performance was significantly improved over the usual overhead of PLI within a verilog simulation.

Logical memories
Denali's MMAV provided the capability to group physical me mory devices together to create a logical memory. This feature was used to group four 16-bit FCRAM devices into a single 64-bit logical memory. In this design, several 64-bit logical memories were generated to provide sufficient storage for the DPC.

These logical memories enabled preloading of a 64-bit data image into a single logical memory, instead of separating the data into smaller 16-bit chunks. They provided full data word backdoor read and write capabilities through Vera. And they generated memory access callbacks on the single logical memory, versus multiple individual callbacks on the physical memory instance. These features resulted in a much simpler and cleaner Vera testbench than would have been possible with other memory model alternatives.

Figure 3 illustrates how the logical memories were created using Vera's built-in Denali User Defined Functions (UDFs). In this example, a Verilog task (DenaliFcramBm) is created to generate a Denali logical memory from the already instantiated phy sical FCRAM devices. This task uses the following Vera's Denali UDFs to generate the logical memory configuration:

• $DENALIstartSysMem - Defines a new logical memory instance named "iSysName" that is comprised of the specified number of physical instances wide, deep and interleaved.
• $DENALIaddSysMem - Adds each physical memory instance to the aforementioned logical memory instance (iSysName).
• $DENALIcreateSysMem - Last step in enabling the logical memory instance. This is called once all the physical instances have been added using DENALIaddSysMem.

Figure 3 - Creating logical memories using Vera code

Memory access callbacks are another key Denali MMAV feature used in the Vera testbench environment. This built-in feature allows users to dynamically "scoreboard" check each memory transaction as it occurs. This mechanism allows users to define a Vera function (access callback function) that will automatically be called when any Denali memory is accessed. This callback function then passes back the memory instance that was accessed, an enumerated access type (such as read, write, masked write, and load), plus the address and data associated with the memory access.

Used in combination with the logical memories created above, this callback will pass back the entire logical address and a 64-bit data word in a single callback, thus significantly simplifying the testbench design and data handling. This feature makes it easy for the Vera testbench to perform checking, scoreboarding, or coverage tasks in response to particular memory transactions. Figure 4 illustrates how this was accomplished.

Figure 4 - Denali memory access callbacks

Summary
Verifying a complex memory subsystem, as is found in a typical line card application, can present unique and interesting challenges. In this design, a new memory technology, FCRAM, was used. Ensuring that the DPC correctly and efficiently accessed this memory was crucial to the application. In addition, the challenges of creating a powerful, yet flexible system verification testbench were numerous. With the aid of Denali's MMAV, which provided accurate memory simulation models and some key verification features, and Synopsys' Vera, which provided a sophisticated and powerful system level testbench, the overall verification time and effort was significantly reduced.

Jeremy Yiu is an ASIC Designer and Verification Expert for AcceLight Networks in Ottawa, Canada since August 2000. Yiu previously worked as a Verification expert for Nortel Networks in Ottawa.